Switch Controls
First Claim
1. A switch comprising:
- an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least 4; and
a bias network includinga control line,for each pair of transistors,a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, disposed in series between the gates of the pair of transistors, andfor two pairs of transistors a second connection including a second node connecting the first nodes, the second node being coupled to the control line.
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Accused Products
Abstract
Switches for use in RF devices are provided that offer a better balance of power losses and switching times than switches of the prior art. Switches of the present invention comprise a stack of transistors controlled a symmetric bias network. The stack of transistors includes an even number of transistors arranged in series, where every two successive transistors defines a pair. The bias network includes a symmetrically branching set of connections, where the gates of every pair of transistors are connected by a first connection having a first node, and two or more first nodes are connected by a second connection to a second node, and so forth. The symmetry of the bias network tends to reject even harmonics, and the rejection of even harmonics can be further enhanced by adding capacitors between the bias network and the stack of transistors at points of symmetry.
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Citations
18 Claims
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1. A switch comprising:
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an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least 4; and a bias network including a control line, for each pair of transistors, a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, disposed in series between the gates of the pair of transistors, and for two pairs of transistors a second connection including a second node connecting the first nodes, the second node being coupled to the control line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An RF device comprising:
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a plurality of power amplifiers; an antenna; and an antenna switch configured to couple one of the plurality of power amplifiers at a time to the antenna, the antenna switch including, for each power amplifier, a serial switch comprising an even number of transistors arranged in series, each transistor of the number of transistors having a source, a drain, and a gate, every two successive transistors defining a pair of transistors, the number of transistors being at least 4; and a bias network including a control line, for each pair of transistors, a first connection, including a first node, connecting the gates of the two transistors, the first connection including two first-level resistors, of equal resistance, disposed in series between the gates of the pair of transistors, and for two pairs of transistors a second connection including a second node connecting the first nodes, the second node being coupled to the control line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification