Displays with Intra-Frame Pause

• US 20150269897A1
• Filed: 05/29/2015
• Published: 09/24/2015
• Est. Priority Date: 02/04/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Lin, Chin-Wei, Huang, Chun-Yao, Chang, Shih Chang, Lee, Szu-Hsien, Kitsomboonloha, Rungrot, Park, Kwang Soon
• Granted Patent: US 9,424,793 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/04184 Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

Claims

1. An electronic device, comprising:

an array of display pixels arranged in rows and columns; and

gate driver circuitry coupled to the array of display pixels, wherein operation of the gate driver circuitry is temporarily suspended during an intra-frame blanking interval, wherein the gate driver circuitry includes a gate driver unit having an output on which a corresponding gate line output signal is provided to display pixels arranged along a corresponding row in the array, and wherein the gate driver unit comprises;

a transistor having a source-drain terminal that is coupled to the output of the gate driver unit and having a gate terminal; and

a pull-down circuit that is coupled to the gate terminal of the transistor and that is turned on during the entirety of the intra-frame blanking interval.

2. The electronic device defined in claim 1, wherein the gate driver unit comprises one gate driver unit in a chain of gate driver units in the gate driver circuitry, and wherein the gate driver unit further comprises:

memory circuitry for buffering gate line output signals from at least one preceding gate driver unit in the chain.

3. The electronic device defined in claim 1, wherein the gate driver unit directly receives a gate line output signal from a non-adjacent gate driver unit in the chain.

4. The electronic device defined in claim 1, wherein the gate driver unit directly receives gate line output signals from at least two different non-adjacent gate driver units in the chain.

5. The electronic device defined in claim 1, wherein the gate driver unit is controlled using two clock signals with different phases.

6. The electronic device defined in claim 2, wherein the memory circuitry comprises a storage capacitor having a terminal that is connected to a power supply terminal.

7. The electronic device defined in claim 6, wherein the memory circuitry further comprises:

a first transistor having a source-drain terminal that is coupled to the gate terminal of the transistor and having a gate terminal; and

a second transistor having a first source-drain terminal that is coupled to another terminal of the storage capacitor and a second source-drain terminal that is coupled to the gate terminal of the first transistor.

8. A display gate driver unit, comprising:

a drive transistor having a drain terminal that receives a clock signal, a source terminal at which a corresponding gate driver output signal is provided, and a gate terminal;

a bootstrapping capacitor having a first terminal that is coupled to the gate terminal of the drive transistor and a second terminal that is coupled to the source terminal of the drive transistor; and

a pull-down transistor that is coupled in series with the drive transistor and that is controlled using a control signal generated at least partly based on the voltage level at the gate terminal of the drive transistor.

9. The display gate driver unit defined in claim 8, wherein the control signal is deasserted whenever the voltage level at the gate terminal of the drive transistor is high.

10. The display gate driver unit defined in claim 8, further comprising:

a first additional pull-down transistor that is coupled to the gate terminal of the drive transistor and that is activated during the entirety of an intra-frame pause (IFP) interval.

11. The display gate driver unit defined in claim 10, further comprising:

a second additional pull-down transistor that is coupled to the gate terminal of the drive transistor and that receives a gate driver output signal from another display gate driver unit.

12. The display gate driver unit defined in claim 8, wherein the display gate driver unit comprises a display gate driver unit in a chain of display gate driver units, and wherein the display gate driver unit further includes:

a first transistor that receives a gate driver output signal from a preceding gate driver unit in the chain; and

a second transistor that is coupled in series with the first transistor at a first intermediate node and that receives a gate driver output signal from a succeeding gate driver unit in the chain.

13. The display gate driver unit defined in claim 12, further comprising:

a storage capacitor having a first terminal that is coupled to the first intermediate node and a second terminal that is coupled to a power supply terminal; and

a third transistor having a first source-drain terminal that is coupled to the first intermediate node, a second source-drain terminal that is coupled to a second intermediate node that is different than the first intermediate node, and a gate terminal that receives an additional clock signal that is different than the clock signal.

14. The display gate driver unit defined in claim 13, further comprising:

a fourth transistor having a gate terminal and a source-drain terminal that receive the additional clock signal;

a fifth transistor having a gate terminal that is coupled to the second intermediate node; and

a sixth transistor that is coupled in series with the fourth and fifth transistors at the gate terminal of the drive transistor.

15. The display gate driver unit defined in claim 14, further comprising:

a seventh transistor having a gate terminal and a source-drain terminal that receive the additional clock signal; and

an eighth transistor that is coupled in series with the seventh transistor and that has a gate terminal that is coupled to the second intermediate node.

16. A method of operating a display gate driver unit that includes a drive transistor having a gate terminal that is coupled to a first intermediate node and a source terminal that is coupled to an output of the display gate driver unit, a first transistor having a gate that is coupled to a second intermediate node and a source terminal that is coupled to the gate terminal of the drive transistor, a second transistor having a first source-drain terminal that is coupled to the second intermediate node and a second source-drain terminal that is coupled to a third intermediate node, a bootstrapping capacitor that is coupled between the gate terminal and the source terminal of the drive transistor, and a storage capacitor that is coupled between the third intermediate node and a ground line, the method comprising:

asserting an enable signal during an intra-frame pause (IFP) interval; and

in response to asserting the enable signal, driving the first intermediate node down towards a low voltage at the ground line.

17. The method defined in claim 16, further comprising:

in response to asserting the enable signal, temporarily reducing the voltage level at the second intermediate node via a voltage kickback mechanism from the first intermediate node.

18. The method defined in claim 16, further comprising:

maintaining the third intermediate node at a constant voltage level when the enable signal is asserted.

19. The method defined in claim 16, further comprising:

receiving a first clock signal at a drain terminal of the drive transistor; and

receiving a second clock signal at a gate terminal of the second transistor, wherein the first and second clock signals are complementary versions of one another.

20. The method defined in claim 19, wherein the display gate driver unit further includes a third transistor that is coupled in series with the first transistor, the method further comprising:

receiving the second clock signal at a gate terminal and a drain terminal of the third transistor.