Bias Control for Stacked Transistor Configuration
First Claim
Patent Images
1. A circuital arrangement comprising:
- i) an amplifier comprising;
stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;
an input port operatively connected to an input transistor of the stacked transistors;
an output port operatively connected to the drain terminal of the output transistor; and
a reference terminal operatively coupling the input transistor to a reference potential, wherein;
the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and
ii) a gate bias circuit,
wherein;
the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a desired voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the desired voltage at the source terminal of the each transistor being in correspondence of a desired distribution of a voltage at the drain terminal of the output transistor across the stacked transistors.
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Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.
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Citations
75 Claims
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1. A circuital arrangement comprising:
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i) an amplifier comprising; stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors; an input port operatively connected to an input transistor of the stacked transistors; an output port operatively connected to the drain terminal of the output transistor; and a reference terminal operatively coupling the input transistor to a reference potential, wherein; the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and ii) a gate bias circuit,
wherein;the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a desired voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the desired voltage at the source terminal of the each transistor being in correspondence of a desired distribution of a voltage at the drain terminal of the output transistor across the stacked transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
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56. A circuital arrangement comprising:
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i) an amplifier comprising; stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors; an input port operatively connected to an input transistor of the stacked transistors; an output port operatively connected to the drain terminal of the output transistor; and a reference terminal operatively coupling the input transistor to a reference potential, wherein; the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and ii) a gate bias circuit,
wherein;the gate bias circuit is configured to operatively provide at a gate terminal of a transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a desired voltage at a source terminal of the transistor, the gate DC offset voltage being based on a gate-to-source voltage of the transistor, and the desired voltage at the source terminal of the transistor being in correspondence of a desired distribution of a voltage at the drain terminal of the output transistor across the stacked transistors. - View Dependent Claims (57, 58, 59, 60, 61, 62)
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63. A method of amplifying a signal in a circuital arrangement, the method comprising:
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providing an amplifier comprising stacked transistors in a cascode configuration; adapting the arrangement to operatively connect a plurality of bias supplies to a plurality of gate terminals of the stacked transistors and to a drain terminal of an output transistor of the stacked transistors; applying an input signal to an input port of the arrangement operatively connected to an input transistor of the stacked transistors; varying the bias supply to the drain terminal of the output transistor; impressing a desired amplification on the input signal to obtain an amplified output signal by varying at least one bias supply of the plurality of bias supplies to a gate terminal of a transistor of the stacked transistors; and based on the varying the at least one bias supply, providing a voltage at the gate terminal of the transistor which is a gate DC offset voltage above a desired voltage at a source terminal of the transistor, the gate DC offset voltage being based on a gate-to-source voltage of the transistor, and the desired voltage at the source terminal of the transistor being based on a desired distribution of a voltage at the drain terminal of the output transistor across the stacked transistors. - View Dependent Claims (64, 65, 66, 67, 68, 69, 70, 71, 72)
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73. A method of amplifying a radio frequency (RF) signal in a circuital arrangement, the method comprising:
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providing an amplifier comprising stacked transistors in a cascode configuration; adapting the arrangement to operatively connect a plurality of bias supplies to a plurality of gate terminals of the stacked transistors and to a drain terminal of an output transistor of the stacked transistors; applying the RF signal to an input port of the arrangement operatively connected to an input transistor of the stacked transistors; varying the bias supply to the drain terminal of the output transistor; impressing a desired amplification on the input signal to obtain an amplified output signal by varying at least one bias supply of the plurality of bias supplies to a gate terminal of a transistor of the stacked transistors other than the input transistor; and maintaining the desired amplification on the input signal by providing a variable bias supply to a gate terminal of the input transistor configured to provide a desired fixed current in correspondence of the desired amplification through the transistor of the stack. - View Dependent Claims (74, 75)
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Specification