System on a Chip with Always-On Processor

• US 20150346001A1
• Filed: 08/13/2014
• Published: 12/03/2015
• Est. Priority Date: 05/29/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Tripathi, Brijesh, Keil, Shane J., Gulati, Manu, Cho, Jung Wook, Machnicki, Erik P., Herbeck, Gilbert H., Millet, Timothy J., de Cesare, Joshua P., Dalal, Anand
• Granted Patent: US 10,031,000 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: A61G 3/061 using ramps
• CPC Class Codes: B60P 1/433 the loading floor or a part thereof being movable to form the ramp
• CPC Class Codes: G01D 9/00 Recording measured values
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Claims

1. An integrated circuit comprising:

a plurality of components; and

a first component coupled to the plurality of components, the first component configured to remain powered on while the plurality of components are powered off, and the first component configured to couple to at least one sensor in a system that includes the integrated circuit, wherein the first component includes a processor, a sensor capture circuit, and a memory, wherein the sensor capture circuit is configured to capture sensor data in the memory from the at least one sensor, and wherein the processor is configured to perform processing on the captured sensor data during a time that the plurality of components are powered down.

2. The integrated circuit as recited in claim 1 wherein the processor is configured to filter the captured sensor data in the memory.

3. The integrated circuit as recited in claim 2 wherein the first component is configured to cause the plurality of components to be powered on in response to the processor detecting a predetermined state in the captured sensor data during the filtering.

4. The integrated circuit as recited in claim 1 wherein the first component is configured to operate at a plurality of power states, and wherein a first power state of the plurality of power states includes the sensor capture circuit being powered on and capturing sensor data while the processor is inactive.

5. The integrated circuit as recited in claim 4 wherein a second power state of the plurality of power states includes the processor being active to perform the processing.

6. The integrated circuit as recited in claim 5 wherein the first component is configured to transition from the first power state to the second power state responsive to the captured sensor data in the memory reaching a predetermined amount.

7. The integrated circuit as recited in claim 4 wherein a second power state of the plurality of power states includes the sensor capture circuit and the processor being inactive.

8. The integrated circuit as recited in claim 7 wherein the first component is configured to transition from the second power state to the first power state responsive to sensor data being available to read.

9. A method comprising:

powering a first component of a plurality of components in an integrated circuit during a time that a remainder of the plurality of components are powered down; and

during the time that the remainder of the plurality of components are powered down, the first component;

capturing sensor data from at least one sensor coupled to the integrated circuit;

filtering the captured sensor data; and

powering up the remainder of plurality of components responsive to the filtering.

10. The method as recited in claim 9 wherein the first component is configured to operate at a plurality of power states, and wherein the capturing occurs at a first power state of the plurality of power states, and wherein the filtering occurs at a second power state of the plurality of states, wherein the method further comprises:

detecting that the captured sensor data is ready for filtering; and

transitioning from the first power state to the second power state responsive to the detecting.

11. The method as recited in claim 10 wherein the first component is further configured to operate at a third power state when idle, wherein the method further comprises:

detecting that the sensor data is ready for capturing; and

transitioning from the third power state to the first power state responsive to the detecting.

12. The method as recited in claim 11 wherein the first component comprises a sensor capture unit, wherein the first state comprises the sensor capture unit being active and a processor within the first component being inactive, wherein transitioning to the second power state comprises activating the processor to perform the filtering.

13. The method as recited in claim 12 wherein the third power state comprises the processor and the sensor capture unit being inactive, wherein transitioning to the first power state comprises activating the sensor capture module.

14. The method as recited in claim 11 further comprising transitioning from the first power state to the third power state responsive to completing the capturing of the sensor data.

15. The method as recited in claim 11 further comprising transitioning from the second power state to one of the first power state and the third power state responsive to completing the filtering.

16. A system comprising:

at least one sensor; and

a system on a chip (SOC) comprising a central processing unit (CPU) complex, a memory controller, and a component that is powered on when a remainder of the SOC, including the CPU complex and the memory controller, is powered off, wherein the component is coupled to the sensor and is configured to capture data from the sensor and filter the captured data during a time that the remainder of the SOC is powered off.

17. The system as recited in claim 16 wherein the sensor is an accelerometer.

18. The system as recited in claim 16 wherein the sensor is a gyroscope.

19. The system as recited in claim 16 wherein the component supports a plurality of power states, wherein different power states of the plurality of power states are used for the data capture and for the filter of the captured data.

20. The system as recited in claim 19 wherein the component is configured to determine that the remainder of the SOC is to be powered up, and wherein the component is configured to cause the SOC to power up responsive to determining that the remainder of the SOC is to power up.