CONTROLLER HAVING ERROR CORRECTION FUNCTION IN ACCORDANCE WITH OPERATING STATE OF MONITORING TARGET

• US 20150365110A1
• Filed: 06/09/2015
• Published: 12/17/2015
• Est. Priority Date: 06/11/2014
• Status: Active Grant

• Current Assignee: Fanuc Corporation
• Original Assignee: Fanuc Corporation
• Inventors: AKIMOTO, Shinji
• Granted Patent: US 9,787,330 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: H03M 13/353 Adaptation to the channel

Abstract

A controller has an error correction capability by including: a state monitoring unit that analyzes a state of a monitoring target and outputs state information; an error correction processing unit that switches error correction codes so that a correction rate for the respective states becomes a value within a predetermined range; and a correction rate calculation unit that calculates the correction rate for the respective states based on the correction result by the error correction processing unit.

Claims

1. A controller that has an error correction function that encodes information data into code words and decodes code words into information data by using error correction codes, and automatically corrects a correctable error in decoding,

The controller comprising:

a state monitoring unit that monitors a state of a monitoring target and outputs state information;

a correction rate calculation unit that outputs a correction rate for respective states; and

an error correction processing unit that has an error correction code group including a plurality of error correction codes having a correction capability ranking, which is defined based on a predetermined standard, encodes information data into code words and decodes code words into information data by switching the error correction codes, and outputs correction information related to the error correction, wherein

the correction rate calculation unit is constituted to calculate the correction rate for the respective states based on the state information outputted by the state monitoring unit and the correction information outputted by the error correction processing unit, and

the error correction processing unit is constructed to switch the error correction codes based on the correction rate for the respective states outputted by the correction rate calculation unit.

2. The controller having an error correction function according to claim 1, further comprising a sequential arithmetic circuit, wherein

the correction rate calculation unit is constructed to calculate the correction rate for the respective states, using the sequential arithmetic circuit.

3. The controller having an error correction function according to claim 1, wherein

the correction rate calculation unit includes a correction information history table that stores the state information and the correction information after linking these items of information, and is constituted to calculate the correction rate for the respective states, based on the state information outputted by the state monitoring unit, the correction information outputted by the error correction processing unit, and the correction information history table.

4. The controller having an error correction function according to claim 1, wherein

the error correction processing unit is constituted so that code words based on one error correction code of the error correction code group can be re-encoded into code words based on another error correction code of the error correction code group.

5. The controller having an error correction function according to claim 1, wherein

the error correction code group includes error correction codes of which correction capability is quantified based on the number of random error-correctable bits.

6. The controller having an error correction function according to claim 1, wherein

the error correction code group includes error correction codes of which correction capability is quantified based on the number of burst error-correctable bits.

7. The controller having an error correction function according to claim 1, wherein

the error correction code group includes error correction codes of which correction capability is quantified based on an encoding rate.

8. The controller having an error correction function according to claim 1, wherein

the state monitoring unit includes:

a state information generation unit that monitors a measurement value by a sensor installed in a monitoring target, determines whether the measurement value is within a predetermined range or not, and generates state information based on the determined result; and

a range change unit that changes the predetermined range.

9. The controller having an error correction function according to claim 1, wherein

the state monitoring unit includes:

a state information generation unit that monitors a program counter of a controller of a machine which executes a control program, determines whether a value of the program counter is within a predetermined program block or not, and generates state information based on the determined result; and

a definition change unit that changes the definition of the predetermined program block.

10. The controller having an error correction function according to claim 1, wherein

the controller includes an error correction code registration/change unit that registers or changes an error correction code in the error correction code group.

11. The controller having an error correction function according to claim 1, wherein

the correction rate calculation unit is constituted to calculate the correction rate for the respective states based on the number of corrected bits in a predetermined period for the respective states.