Method of Semiconductor Integrated Circuit Fabrication

• US 20160027692A1
• Filed: 10/05/2015
• Published: 01/28/2016
• Est. Priority Date: 10/30/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shieh, Ming-Feng, Hsieh, Hung-Chang, Tseng, Wen-Hung
• Granted Patent: US 10,672,656 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28141 insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/4763 Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28, H01L21/44
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76861 Post-treatment or after-treatment not introducing additional chemical elements into the layer
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 : manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 : interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823821 : with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 : with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823864 : with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823871 : interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 : isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/485 : consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53233 : Copper alloys
• CPC Class Codes: H01L 23/53257 : the principal metal being a refractory metal
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/41775 : characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/435 : Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/4958 : with a multiple layer structure
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Claims

1. A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

providing a first conductive feature and a second conductive feature on a substrate, separated by a first dielectric layer;

forming a first hard mask (HM) as a top layer on the first conductive feature;

forming a first patterned dielectric layer over the first and the second conductive features, wherein the first patterned dielectric layer has a first opening to expose the second conductive feature;

forming a first metal plug in the first opening to connect the second conductive feature;

forming a second HM as a top layer on the first metal plug;

forming a second patterned dielectric layer over the first conductive feature and the first metal plug, wherein the second patterned dielectric layer has second openings to expose the first conductive feature and a subset of the first metal plugs; and

forming second metal plugs in the second openings to connect to the first conductive feature and the subset of the first metal plugs.

2. The method of claim 1, wherein the forming of the first HM includes:

recessing the first conductive feature to form a first trench;

depositing a first HM layer over the substrate, including a first portion filling in the first trench and a second portion extending beyond the first trench; and

removing the second portion of the first HM layer.

3. The method of claim 1, wherein the forming of the first patterned dielectric layer includes:

depositing a second dielectric layer over the first dielectric layer;

forming a photoresist pattern over the second dielectric layer; and

selectively etching the second and the first dielectric layers through the photoresist pattern, wherein the selective etch has selectivity with respect to the first hard mask.

4. The method of claim 1, wherein the forming of the second HM includes:

recessing the first metal plug to form a second trench;

depositing a second HM layer over the substrate, including a first portion filling in the second trench and a second portion extending beyond the second trench; and

removing the second portion of the second HM layer.

5. The method of claim 1, wherein the first conductive feature includes a gate stack.

6. The method of claim 5, wherein the second conductive feature includes a source/drain region

7. A method comprising:

receiving a substrate having a first dielectric layer disposed thereupon, a first conductive feature disposed within the first dielectric layer, a first hard mask disposed on the first conductive feature, and a second conductive feature disposed within the substrate;

recessing a portion of the first dielectric layer to define a second trench that exposes the second conductive feature;

forming a first plug in the second trench and electrically coupled to the second conductive feature;

recessing a portion of the first plug to define a third trench;

forming a second hard mask within the third trench;

forming a second plug that extends through the second hard mask to electrically couple to the first plug; and

forming a third plug that extends through the first hard mask to electrically couple to the first conductive feature.

8. The method of claim 7, wherein the first conductive feature includes a gate feature.

9. The method of claim 8, wherein the second conductive feature includes a source/drain feature.

10. The method of claim 7, wherein the recessing of the first dielectric layer to define the second trench uses an etchant selected to avoid etching of the first hard mask to expose the first conductive feature.

11. The method of claim 7, wherein the recessing of the portion of the first dielectric layer includes:

forming a second dielectric layer on the first dielectric layer; and

recessing a portion of the second dielectric layer such that the second trench extends through the second dielectric layer and the first dielectric layer to expose the second conductive feature.

12. The method of claim 7, wherein the forming of the second plug includes:

forming a second dielectric layer on the first dielectric layer;

recessing a portion of the second dielectric layer and the second hard mask to define a fourth trench that exposes the first plug; and

depositing the second plug within the fourth trench.

13. The method of claim 12, wherein the forming of the third plug includes:

recessing the second dielectric layer and the first hard mask to define a fifth trench that exposes the first conductive feature; and

depositing the third plug within the fifth trench.

14. The method of claim 7, wherein a top surface of the first dielectric layer is substantially coplanar with a top surface of the first hard mask layer.

15. A method comprising:

receiving a substrate having disposed thereupon;

a first conductive feature and a second conductive feature, wherein a top surface of the first conductive feature is above a top surface of the second conductive feature in a horizontal direction; and

a first dielectric layer disposed alongside the first conductive feature and on the second conductive feature;

forming a first hard mask on the first conductive feature, wherein a top surface of the first hard mask is substantially coplanar with a top surface of the first dielectric layer;

forming a first trench in the first dielectric layer that exposes the second conductive feature;

forming a first plug in the first trench and on the second conductive feature;

forming a second hard mask on the first plug;

forming a second plug that extends through the second hard mask and coupled to the first plug; and

forming a third plug that extends through the first hard mask and coupled to the first conductive feature.

16. The method of claim 15, wherein the first conductive feature includes a gate stack.

17. The method of claim 16, wherein the second conductive feature includes a source/drain feature.

18. The method of claim 15, wherein the forming of the first trench uses an etchant composition selected to avoid substantial etching of the first hard mask.

19. The method of claim 15, wherein the forming of the first trench includes forming a second dielectric layer over the first dielectric layer, and wherein the first trench extends though the second dielectric layer and the first dielectric layer.

20. The method of claim 15, wherein a top surface of the second hard mask is substantially coplanar with the top surface of the first hard mask.