INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
First Claim
1. A method for manufacturing an interconnect structure, comprising:
- forming a via opening and a line trench in a dielectric layer, wherein a width of the via opening and a width of the line trench are in a range of from about 1.0 nm to about 50 nm;
forming a 1-dimensional conductive feature in the via opening;
forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature;
removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature; and
forming a 2-dimensional conductive feature in the line trench.
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Abstract
The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.
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Citations
20 Claims
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1. A method for manufacturing an interconnect structure, comprising:
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forming a via opening and a line trench in a dielectric layer, wherein a width of the via opening and a width of the line trench are in a range of from about 1.0 nm to about 50 nm; forming a 1-dimensional conductive feature in the via opening; forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature; removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature; and forming a 2-dimensional conductive feature in the line trench. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for manufacturing a semiconductor structure, comprising:
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forming a via opening and a line trench in a dielectric layer, the line trench being wider than the via opening; forming a first conductive feature in the via opening; forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the first conductive feature; removing the conformal catalyst layer from the bottom of the line trench and the top of the first conductive feature; and forming a second conductive feature in the line trench. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method for manufacturing an interconnect structure, comprising:
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forming a via opening having a first aspect ratio in a first dielectric layer; forming a line trench having a second aspect ratio over the via, opening in a second dielectric layer, the first aspect ratio being equivalent to or greater than the second aspect ratio; forming a first conductive feature in the via opening; forming a conformal catalyst layer over the line trench, a bottom of the line trench, and a top of the first conductive feature; removing the conformal catalyst layer from the bottom of the line trench and the top of the first conductive feature; and forming a second conductive feature in the line trench. - View Dependent Claims (17, 18, 19, 20)
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Specification