VERTICAL GATE-ALL-AROUND TFET

• US 20160293739A1
• Filed: 06/08/2016
• Published: 10/06/2016
• Est. Priority Date: 03/31/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: ZHANG, John H.
• Granted Patent: US 9,653,585 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66909 : Vertical transistors, e.g. tecnetrons
• CPC Class Codes: H01L 29/66977 : Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7855 : with at least two independent gates
• CPC Class Codes: H01L 29/7856 : with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 31/0392 : including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate textured substrates H01L31/02366
• CPC Class Codes: H01L 33/04 : with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

Claims

1. A device, comprising:

a silicon substrate;

a diode on the substrate, the diode including;

a doped well in the silicon substrate;

a nanowire on the substrate extending from the doped well;

a first contact is formed on a first end of the nanowire; and

a second contact is formed adjacent to a second end of the nanowire, where the second end of the nanowire is adjacent to the doped well.

2. The device of claim 1 wherein the doped well is between the second contact and the second end of the nanowire.

3. The device of claim 1 wherein the nanowire is doped to have a polarity opposite that of the doped well.

4. The device of claim 1 wherein the first contact has a narrow portion adjacent to the first end of the nanowire and a wider portion on the narrow portion.

5. The device of claim 4 wherein the first contact is T-shaped.

6. The device of claim 1 wherein the nanowire include a middle portion between the first and second ends and the first contact has a narrow portion adjacent to the first end of the nanowire and a wider portion adjacent to the middle portion of the nanowire.

7. A device, comprising:

a silicon substrate;

a first well in the silicon substrate;

a second well in the substrate;

an isolation region in the substrate between the first and second wells;

a first nanowire extending from the first well away from the substrate;

a second nanowire extending from the second well away from the substrate;

a first contact on the first nanowire;

a second contact on the second nanowire;

a third contact adjacent to the first well; and

a fourth contact adjacent to the second well.

8. The device of claim 7 wherein the first well separates the first nanowire from the third contact.

9. The device of claim 8 wherein the second well separates the second nanowire from the fourth contact.

10. The device of claim 7 wherein the first and second contacts have a narrow portion adjacent to the first and second nanowire, respectively, and a wider portion on the narrow portion.

11. A device, comprising:

a substrate;

a first contact on a first surface of the substrate;

a nanowire extending from a second surface of the substrate;

a doped region in the substrate between the first contact and the nanowire; and

a second contact on the nanowire spaced from the doped region, the second contact having a narrow portion and a wider portion.

12. The device of claim 11 wherein the second contact is T-shaped.

13. The device of claim 11 further comprising an encapsulant around the nanowire.

14. The device of claim 13, further comprising a dielectric on the encapsulant and around the second contact.

15. The device of claim 14 wherein the wider portion of the second contact is closer to the encapsulant than the narrow portion of the second contact.