VERTICAL GATE-ALL-AROUND TFET
First Claim
1. A device, comprising:
- a silicon substrate;
a diode on the substrate, the diode including;
a doped well in the silicon substrate;
a nanowire on the substrate extending from the doped well;
a first contact is formed on a first end of the nanowire; and
a second contact is formed adjacent to a second end of the nanowire, where the second end of the nanowire is adjacent to the doped well.
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Accused Products
Abstract
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
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Citations
15 Claims
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1. A device, comprising:
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a silicon substrate; a diode on the substrate, the diode including; a doped well in the silicon substrate; a nanowire on the substrate extending from the doped well; a first contact is formed on a first end of the nanowire; and a second contact is formed adjacent to a second end of the nanowire, where the second end of the nanowire is adjacent to the doped well. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A device, comprising:
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a silicon substrate; a first well in the silicon substrate; a second well in the substrate; an isolation region in the substrate between the first and second wells; a first nanowire extending from the first well away from the substrate; a second nanowire extending from the second well away from the substrate; a first contact on the first nanowire; a second contact on the second nanowire; a third contact adjacent to the first well; and a fourth contact adjacent to the second well. - View Dependent Claims (8, 9, 10)
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11. A device, comprising:
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a substrate; a first contact on a first surface of the substrate; a nanowire extending from a second surface of the substrate; a doped region in the substrate between the first contact and the nanowire; and a second contact on the nanowire spaced from the doped region, the second contact having a narrow portion and a wider portion. - View Dependent Claims (12, 13, 14, 15)
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Specification