DISPLAY PANEL AND PIXEL ARRAY THEREOF

• US 20160370636A1
• Filed: 02/19/2016
• Published: 12/22/2016
• Est. Priority Date: 06/16/2015
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Huang, Shiuan-Hua, Lin, Jian-Hong
• Granted Patent: US 9,778,526 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A pixel array includes pixel rows. Each pixel row includes a first gate line, a second gate line, sub-pixels and data lines. Each data line includes a main portion, a branch portion and a connecting portion. The main portions of the data lines are arranged along a second direction in sequence. The branch portions and the main portions of the data lines are arranged alternately along the second direction in sequence, and each sub-pixel is disposed between any two of the adjoining main portion and branch portion. The connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each data line is electrically connected with the main portion and the branch portion of each data line, and the connecting portion of each data line penetrates through the corresponding sub-pixel along the second direction.

Claims

1. A pixel array disposed on an array substrate, the pixel array comprising:

a plurality of pixel rows, each of the pixel rows comprising;

a first gate line;

a second gate line, wherein the first gate line and the second gate line are arranged alternately along a first direction in sequence;

a plurality of sub-pixels disposed between the first gate line and the second gate line along a second direction, wherein a portion of the sub-pixels are electrically connected with the first gate line, and the other portion of the sub-pixels are electrically connected with the second gate line; and

a plurality of data lines, each of the data lines comprising a main portion, a branch portion and a connecting portion, wherein;

the main portions of the data lines are arranged along the second direction in sequence, and the main portions of the data lines intersect the first gate line and the second gate line;

the branch portions and the main portions of the data lines are arranged alternately along the second direction, and each of the sub-pixels is disposed between any two of the main portion and the branch portion adjoining to each other; and

the connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each of the data lines is electrically connected with the main portion and the branch portion, and the connecting portion of each of the data lines penetrates through the sub-pixel disposed between the main portion and the branch portion along the second direction.

2. The pixel array according to claim 1, wherein the pixel rows comprise a first pixel row and a second pixel row, the connecting portions of the data lines penetrate even-numbered sub-pixels of the plurality of sub-pixels of the first pixel row, and the connecting portions of the data lines penetrate odd-numbered sub-pixels of the plurality of sub-pixels of the second pixel row.

3. The pixel array according to claim 1, wherein each of the sub-pixels comprises an active switching device and a pixel electrode, the active switching device comprises a gate electrode, a drain electrode and a source electrode, and the pixel electrode is electrically connected with the drain electrode of the active switching device.

4. The pixel array according to claim 3, wherein in each of the pixel rows, the gate electrodes of the active switching devices of (6n−

5)^th numbered sub-pixels of the plurality of sub-pixels, the gate electrodes of the active switching devices of (6n−

2)^th numbered sub-pixels of the plurality of sub-pixels and the gate electrodes of the active switching devices of (6n)^th numbered sub-pixels of the plurality of sub-pixels are electrically connected with the first gate line, the gate electrodes of the active switching devices of (6n−

4)^th numbered sub-pixels of the plurality of sub-pixels, the gate electrodes of the active switching devices of (6n−

3)^th numbered sub-pixels of the plurality of sub-pixels and the gate electrodes of the active switching devices of (6n−

1)^th numbered sub-pixels of the plurality of sub-pixels are electrically connected with the second gate line, and n is a set of integers greater than 0.

5. The pixel array according to claim 4, wherein the branch portion is electrically connected with the source electrodes of the active switching devices of two sub-pixels of the plurality of sub-pixels respectively adjoining to the branch portion in the second direction.

6. The pixel array according to claim 1, further comprising a passivation layer, an insulating layer and a common electrode disposed on the array substrate, wherein the common electrode is disposed on the passivation layer, the pixel electrodes are disposed on the common electrode, and the insulating layer is disposed between the common electrode and the pixel electrodes.

7. The pixel array according to claim 6, wherein each of the pixel rows further comprises a common line disposed between the first gate line and the second gate line, the common line at least partially overlaps the connecting portions of the data lines in a vertical projection direction, and the common line is electrically connected with the common electrode.

8. The pixel array according to claim 7, wherein the common line is disposed between the insulating layer and the common electrode.

9. The pixel array according to claim 6, further comprising a plurality of common lines, wherein each of the common lines is disposed between the second gate line of one of the pixel rows and the first gate line of another one of the pixel row adjoining thereto, and the common lines are electrically connected with the common electrode.

10. The pixel array according to claim 9, wherein the common lines are disposed between the insulating layer and the common electrode.

11. A display panel, comprising:

the pixel array according to claim 1;

a counter substrate disposed opposite to the array substrate; and

a display medium layer disposed between the array substrate and the counter substrate.