INTERFACE ADJUSTMENT PROCESSES FOR A DATA STORAGE DEVICE

• US 20170031845A1
• Filed: 07/29/2015
• Published: 02/02/2017
• Est. Priority Date: 07/29/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: TZAFRIR, YONATAN
• Granted Patent: US 10,101,763 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence

Abstract

A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

Claims

1. A method comprising:

in a data storage device that includes a controller and a memory die, wherein the controller includes a host interface and a memory interface, performing by the controller;

receiving a message from a host device via the host interface, the message indicating that the host device is to perform a first adjustment process associated with the host interface; and

performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

2. The method of claim 1, wherein the message includes a command that complies with an embedded MultiMedia Card (eMMC) standard.

3. The method of claim 1, wherein the message includes a command that complies with a Serial Advanced Technology Attachment (SATA) standard.

4. The method of claim 1, wherein the message includes a command that complies with a Universal Serial Bus (USB) standard.

5. The method of claim 1, wherein the second adjustment process includes writing data to a memory of the memory die in response to the message indicating that the host device is to initiate the first adjustment process, and wherein the second adjustment process includes reading the data from the memory in response to the message indicating that the host device is to initiate the first adjustment process.

7. The method of claim 5, further comprising:

prior to sending the data to the memory, encoding the data at an error correction code (ECC) engine of the data storage device; and

after reading the data from the memory, decoding the data at the ECC engine.

8. The method of claim 1, wherein the second adjustment process includes sending data to a latch of the memory die, and wherein the second adjustment process includes retrieving the data from the latch.

10. The method of claim 1, wherein the second adjustment process includes adjusting a phase of a timing signal associated with the memory interface.

11. The method of claim 1, wherein the second adjustment process further includes receiving data from the host device via the host interface during the first adjustment process.

12. The method of claim 11, wherein the second adjustment process includes writing the data to a memory of the memory die and reading the data from the memory.

13. The method of claim 1, wherein the host device performs the first adjustment process to calibrate communications with the data storage device via the host interface, and wherein the controller performs the second adjustment process to enable the first adjustment process to compensate for effects on the host interface that are due to operations at the memory interface.

15. The method of claim 1, wherein the host device performs the first adjustment process to calibrate a phase of a first timing signal associated with the host interface and the controller performs the second adjustment process to calibrate a phase of a second timing signal associated with the memory interface.

6. (canceled)

9. (canceled)

14. (canceled)

16-20. -20. (canceled)

21. A data storage device comprising:

a memory device; and

a controller coupled to the memory device, the controller including a host interface and a memory interface, the controller configured to receive a message from a host device via the host interface, the message indicating that the host device is to perform a first adjustment process associated with the host interface, the controller further configured to perform a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

22. The data storage device of claim 21, further comprising:

a comparator configured to detect the message, wherein the first adjustment process comprises a first calibration process associated with the host interface; and

a phase calibrator configured to initiate the second adjustment process in response to the message indicating that the host device is to initiate the first adjustment process, wherein the second adjustment process comprises a second calibration process associated with the memory interface.

23. The data storage device of claim 21, further comprising a timing device, wherein the controller is further configured to adjust a phase of a timing signal associated with the memory interface using the timing device during the second adjustment process.

24. The data storage device of claim 23, wherein the controller is further configured to generate a clock signal or a strobe signal, and wherein the timing signal includes the clock signal or the strobe signal.

25. The data storage device of claim 23, wherein the memory device is configured to generate a read enable signal, and wherein the timing signal includes the read enable signal.

26. The data storage device of claim 21, wherein the memory device includes a non-volatile memory having a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.

27. An apparatus comprising:

means for receiving a message from a host device, the message indicating that the host device is to perform a first adjustment process associated with the means for receiving; and

means for performing a second adjustment process in response to receiving the message indicating that the host device is to perform the first adjustment process.

28. The apparatus of claim 27, further comprising:

means for storing data, wherein the second adjustment process includes reading the data in response to the message indicating that the host device is to perform the first adjustment process; and

means for decoding the data after the data is read from the means for storing.