STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES

• US 20170047416A1
• Filed: 10/26/2016
• Published: 02/16/2017
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Abhijit Jayant Pethe, Annalisa Cappellani, Harry Gomez, Tahir Ghani
• Original Assignee: Abhijit Jayant Pethe, Annalisa Cappellani, Harry Gomez, Tahir Ghani
• Inventors: Cappellani, Annalisa, Pethe, Abhijit Jayant, Ghani, Tahir, Gomez, Harry
• Granted Patent: US 10,229,981 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;

a three-dimensional channel region disposed above the isolation pedestal;

source and drain regions disposed on either side of the three-dimensional channel region; and

a gate electrode stack surrounding the three-dimensional channel region with a portion disposed on the non-planar uppermost surface of the isolation pedestal.

2. The semiconductor device of claim 1, wherein the source and drain regions are disposed on an epitaxial seed layer, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional channel region and disposed on the non-planar uppermost surface of the isolation pedestal.

3. The semiconductor device of claim 1, further comprising:

a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the non-planar uppermost surface of the isolation pedestal

4. The semiconductor device of claim 2, further comprising:

a pair of insulating spacers, one spacer disposed between the gate electrode stack and the source region, and the other spacer disposed between the gate electrode stack and the drain region, wherein the epitaxial seed layer extends underneath each of the pair of spacers.

5. The semiconductor device of claim 2, further comprising:

a pair of conducting contacts, one contact disposed on and partially surrounding the source region, and the other contact disposed on and partially surrounding the drain region.

6. A semiconductor device, comprising:

a semiconductor substrate;

an isolation pedestal disposed above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;

a three-dimensional channel region disposed above the isolation pedestal;

a gate electrode stack at least partially surrounding the three-dimensional channel region;

source and drain regions disposed on either side of the three-dimensional channel region and above isolation pedestal; and

a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the non-planar uppermost surface of the isolation pedestal.

7. The semiconductor device of claim 6, wherein the three-dimensional channel region is disposed on an epitaxial seed layer disposed on the non-planar uppermost surface of the isolation pedestal, the epitaxial seed layer comprising a semiconductor material different from the three-dimensional channel region, and wherein the gate electrode stack only partially surrounds the three-dimensional channel region.

8. The semiconductor device of claim 7, further comprising:

a pair of insulating spacers, one spacer disposed between the gate electrode stack and the source region, and the other spacer disposed between the gate electrode stack and the drain region, wherein the epitaxial seed layer extends underneath each of the pair of spacers.

9. The semiconductor device of claim 6, further comprising:

one or more nanowires disposed in a vertical arrangement above the three-dimensional channel region, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.

10. A semiconductor structure, comprising:

a semiconductor substrate;

an isolation pedestal above the semiconductor substrate, the isolation pedestal having a unitary body with a non-planar uppermost surface;

a semiconductor body above the isolation pedestal;

a first source or drain region at a first side of the semiconductor body;

a second source or drain region at a second side of the semiconductor body, the second side opposite the first side;

a gate electrode stack at least partially surrounding the semiconductor body;

a first conducting contact on and at least partially surrounding the first source or drain region; and

a second conducting contact on and at least partially surrounding the second source or drain region.

11. The semiconductor structure of claim 10, wherein the gate electrode stack is completely surrounding the semiconductor body, and wherein a portion of the gate electrode stack is on the non-planar uppermost surface of the isolation pedestal.

12. The semiconductor structure of claim 11, wherein the first conducting contact is completely surrounding the first source or drain region, and the second conducting contact is completely surrounding the second source or drain region, and wherein a portion of the first conducting contact and a portion of the second conducting contact is on the non-planar uppermost surface of the isolation pedestal.

13. The semiconductor structure of claim 10, wherein the first conducting contact is completely surrounding the first source or drain region, and the second conducting contact is completely surrounding the second source or drain region, and wherein a portion of the first conducting contact and a portion of the second conducting contact is on the non-planar uppermost surface of the isolation pedestal.

14. The semiconductor structure of claim 10, wherein the gate electrode stack is only partially surrounding the semiconductor body.

15. The semiconductor structure of claim 14, wherein the first conducting contact is completely surrounding the first source or drain region, and the second conducting contact is completely surrounding the second source or drain region, and wherein a portion of the first conducting contact and a portion of the second conducting contact is on the non-planar uppermost surface of the isolation pedestal.

16. The semiconductor structure of claim 14, wherein the first conducting contact is only partially surrounding the first source or drain region, and the second conducting contact is only partially surrounding the second source or drain region.

17. The semiconductor structure of claim 10, wherein the first conducting contact is only partially surrounding the first source or drain region, and the second conducting contact is only partially surrounding the second source or drain region.

18. The semiconductor structure of claim 11, wherein the first conducting contact is only partially surrounding the first source or drain region, and the second conducting contact is only partially surrounding the second source or drain region.

19. The semiconductor structure of claim 10, further comprising:

a first insulating spacer between a first side of the gate electrode stack and the first source or drain region; and

a second insulating spacer between a second side of the gate electrode stack and the second source or drain region, the second side of the gate electrode stack opposite the first side of the gate electrode stack.

20. The semiconductor structure of claim 10, wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode.