SUBSTRATE SUPPORT WITH REAL TIME FORCE AND FILM STRESS CONTROL

• US 20170076915A1
• Filed: 09/11/2015
• Published: 03/16/2017
• Est. Priority Date: 09/11/2015
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: BOYD, Wendell Glen Jr., RAJ, Govinda, BUSCHE, Matthew James
• Granted Patent: US 10,879,046 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: C23C 16/4586 Elements in the interior of the support, e.g. electrodes, heating or cooling devices
• CPC Class Codes: G01D 11/245 Housings for sensors
• CPC Class Codes: G01D 5/26 characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
• CPC Class Codes: G01D 5/266 by interferometric means G01D5/353 takes precedence
• CPC Class Codes: G01D 5/268 using optical fibres G01D5/28 - G01D5/38 take precedence
• CPC Class Codes: G01L 11/025 using a pressure-sensitive optical fibre
• CPC Class Codes: H01J 2237/334 Etching
• CPC Class Codes: H01J 37/32009 Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources plasma generation in general H05H1/24
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01J 37/32697 Electrostatic control
• CPC Class Codes: H01J 37/32715 Workpiece holder
• CPC Class Codes: H01J 37/3299 Feedback systems
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/6833 Details of electrostatic chucks

Abstract

Embodiments disclosed herein include a substrate support having a sensor assembly, and processing chamber having the same. In one embodiment, a substrate support has a puck. The puck has a workpiece support surface and a gas hole exiting the workpiece support surface. A sensor assembly is disposed in the gas hole and configured to detect a metric indicative of a deflection of a workpiece disposed on the workpiece support surface, wherein the sensor assembly is configured to allow gas to flow past the sensor assembly when positioned in the gas hole.

Claims

1. A method for forming high aspect ratio features in a gate electrode layer in a gate structure, the method comprising:

performing an surface treatment process on gate electrode residuals remaining on a gate structure disposed on a substrate;

selectively forming a treated residual on the gate structure on the substrate with untreated regions nearby on the gate structure; and

performing a remote plasma residual removal process to remove the treated residual from the substrate.

2. The method of claim 1, wherein performing the remote plasma residual removal process further comprises:

forming a remote plasma from a gas mixture including a hydrogen-containing gas.

3. The method of claim 2, wherein the hydrogen-containing gas is H2.

4. The method of claim 1, wherein performing the surface treatment process comprises:

supplying a treatment gas mixture including an inert gas.

5. The method of claim 1, wherein forming the treated region further comprises:

forming an amorphous film structure in the treated residual in response to a change in the lattice structure of the gate electrode layer caused by atoms from the inert gas. cm 6. The method of claim 1, wherein the treated residual forms an amorphous silicon material.

7. The method of claim 1, wherein the treated residual and the untreated region have different etching rate, providing an etching selectivity during the residual removal process.

8. The method of claim 1, wherein the gate electrode layer is a polysilicon layer.

9. The method of claim 4, wherein the inert gas is Ar gas or Ne gas.

10. The method of claim 1, wherein performing the remote plasma residual removal process further comprises:

maintaining a substrate temperature greater than 200 degrees Celsius.

11. The method of claim 1, wherein performing the surface treatment process further comprising:

supplying a RF bias power during the surface treatment process without RF source power.

12. The method of claim 1, wherein the gate electrode residuals are formed a corner between sidewalls of a gate electrode and a surface of a gate dielectric layer disposed in the gate structure.

13. The method of claim 12, wherein the gate dielectric layer is a silicon oxide layer, silicon nitride layer, silicon oxynitride layer, high-k materials, or combinations thereof.

14. The method of claim 1, further comprising:

performing a gate electrode layer etching process prior to performing the surface treatment process, leaving some gate electrode residuals on the substrate.

15. The method claim 14, wherein the gate electrode layer etching process, the treatment process, and the remote plasma residual removal process are performed in a single chamber.

16. The method of claim 14, further comprising:

forming features with high aspect ratio greater than 10;

1 in the gate electrode layer with gate electrode residuals remaining on the substrate.

17. The method of claim 1, further comprising:

cyclically performing the surface treatment process and the residual removal process until the gate electrode residuals are substantially removed from the substrate.

18. A method for forming high aspect ratio features in a gate electrode layer in a gate structure, the method comprising:

altering film properties of gate electrode residuals on a gate structure formed on a substrate; and

selectively removing the gate electrode residuals from the substrate.

19. The method of claim 18, wherein altering film properties of the gate electrode residuals further comprises:

performing a surface treatment process by supplying an inert gas into a processing chamber where the substrate is disposed.

20. The method of claim 18, wherein selectively removing the gate electrode residuals further comprising:

performing a remote plasma residual removal process by supplying a treatment gas mixture including hydrogen-containing gas from a remote plasma source.

21. A method for forming high aspect ratio features in a gate electrode layer in a gate structure, the method comprising

selectively treating gate electrode residuals remaining on a substrate after patterning a gate electrode layer disposed in a gate structure formed on a substrate;

and

selectively removing the treated gate electrode residuals from the gate structures by a remote plasma source generated from a gas mixture containing H2 gas.