MULTI-PHASE CURRENT MODE CONTROL LOOP INCORPORATING A DISTRIBUTED TRANSCONDUCTANCE STAGE

• US 20170090501A1
• Filed: 09/30/2015
• Published: 03/30/2017
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Gozzini, Fabio, Fletcher, Jay B., Searles, Shawn, Pant, Sanjay
• Granted Patent: US 10,520,970 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/08 wherein the variable is dc
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved

Abstract

A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to a common output node. Each of the phase units may be configured to source current to the output node in response to the assertion of a respective clock signal in order to generate a regulated supply voltage. Each phase unit includes a respective transconductance amplifier configured to generate a respective demand current dependent upon a reference voltage and the regulated supply voltage.

Claims

1. An apparatus, comprising:

a first phase unit including a first transconductance amplifier, wherein the first phase unit is configured to generate a regulated supply voltage dependent upon a first clock signal;

wherein the first transconductance amplifier is configured to generate a first current dependent upon a reference voltage and the regulated supply voltage; and

a second phase unit including a second transconductance amplifier, wherein the second phase unit is configured to generate the regulated supply voltage dependent upon a second clock signal;

wherein the second transconductance amplifier is configured to generate a second current dependent upon the reference voltage and the regulated supply voltage.

2. The apparatus of claim 1, wherein to generate the regulated supply voltage, the first phase unit is further configured to compare the first current to a first sense current, wherein the first sense current corresponds to a current sourced to a first inductor included in the first phase unit, and wherein to generate the regulated supply voltage, the second phase unit is further configured to compare the second current to a second sense current, wherein the second sense current corresponds to a current source to a second inductor included in the second phase unit.

3. The apparatus of claim 2, wherein the first phase unit includes a first driver circuit configured to source current to the first inductor dependent upon the first clock signal, and sink current from the first inductor dependent upon a comparison of the first demand current and the first source current.

4. The apparatus of claim 1, wherein a phase of the first clock signal is different than a phase of the second clock signal.

5. The apparatus of claim 1, further comprising a reference generator unit configured to generate the reference voltage.

6. The apparatus of claim 1, further comprising a clock generator unit configured to generate the first clock signal and the second clock signal dependent upon a system clock signal.

7. A method for operating a voltage regulator unit, the method comprising:

initiating a first charge cycle of a first phase unit of a plurality of phase units dependent upon a first clock signal of plurality of clock signals, wherein each phase of the plurality of phase units is coupled to a load circuit;

sourcing a first current to the load circuit by the first phase unit during the charge cycle of the first phase unit;

generating, by a first transconductance amplifier of the first phase unit, a second current dependent upon a voltage level at an output of the voltage regulator unit and a reference voltage level; and

initiating a discharge cycle of the first phase unit dependent upon a comparison of the first current and the second current.

8. The method of claim 7, further comprising initiating a second charge cycle of a second phase unit of the plurality of phase units dependent upon a second clock signal of the plurality of clock signals.

9. The method of claim 7, further comprising generating, by a second transconductance amplifier included in the second phase unit, a third current dependent upon the voltage level at the output of the voltage regulator unit and the reference voltage level.

10. The method of claim 7, wherein an assertion of the second clock signal occurs after a predetermined period of time has elapsed since an assertion of the first clock signal.

11. The method of claim 7, wherein a value of the second current is proportional to a difference between the voltage level at the output of the voltage regulator unit and the reference voltage level.

12. The method of claim 7, wherein the first phase unit comprises setting a latch in response to an assertion of the first clock signal.

13. The method of claim 7, wherein the plurality of phase units are each included in a common integrated circuit package.

14. A system, comprising:

a plurality of functional units, wherein at least one functional unit is coupled to a regulated power supply; and

a regulator unit including a plurality of phase units, wherein a given phase unit of the plurality of phase units is configured to;

enable a transistor included a respective driver circuit coupled to regulated power supply dependent upon a respective one of a plurality of clock signals;

generate, using a respective transconductance amplifier, a respective demand current dependent upon a reference voltage and a voltage level of the regulated power supply; and

disable the transistor included in the respective driver circuit dependent upon a comparison of the respective demand current and a respective source current.

15. The system of claim 14, wherein to enable the transistor included in the respective driver circuit, the given phase unit is further configured to set a latch circuit in response to an assertion of the respective one of the plurality of clock signals.

16. The system of claim 14, wherein each functional unit of the plurality of functional units and the regulator unit are included in a common integrated circuit package.

17. The system of claim 14, wherein each functional unit of the plurality of functional units and the regulator unit are included on a single integrated circuit.

18. The system of claim 14, wherein the regulator unit includes a reference generator configured to generate the reference voltage.

19. The system of claim 14, wherein a phase of a given clock signal of the plurality of clock signals is different than a respective phase of remaining clock signals of the plurality of clock signals.

20. The system of claim 14, wherein the regulator unit includes a clock generator unit configured to generate the each clock signal of the plurality of clock signals.