Semiconductor ESD Protection Device and Method
First Claim
Patent Images
1. An electrostatic discharge (ESD) protection circuit comprising:
- a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal; and
a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor.
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Abstract
According to an embodiment, an electrostatic discharge (ESD) protection circuit includes a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal. The ESD protection circuit further includes a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor.
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Citations
24 Claims
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1. An electrostatic discharge (ESD) protection circuit comprising:
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a first transistor having a first source/drain coupled to a first input/output terminal, a second source/drain coupled to a first reference voltage terminal, and a gate coupled to a second reference voltage terminal; and a direct current (DC) blocking circuit having a first input/output node coupled to the first input/output terminal, a second input/output node configured to be coupled to a useful circuit, and a third input/output node coupled a gate of the first transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit comprising:
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an input pad; a useful circuit; and an electrostatic discharge (ESD) protection circuit coupled between the input pad and an input/output terminal of the useful circuit, the ESD protection circuit comprising a direct current (DC) blocking circuit coupled between the input pad and the input/output terminal of the useful circuit, and a first transistor having a first source/drain coupled to the input pad, a second source/drain coupled to the ground, and a gate coupled to the DC blocking circuit at a first node; and a reference voltage source coupled to the gate of the first transistor at the first node, the reference voltage source providing a reference voltage to turn the first transistor off. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method comprising:
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applying a first voltage between a gate terminal and a first source/drain terminal of a first transistor, the first transistor having the first source/drain terminal coupled to a first power supply node and a second source/drain terminal coupled to an input pad of an integrated circuit, wherein the first voltage an a threshold voltage of the first transistor have opposite polarities; receiving an ESD pulse of a first polarity at the input pad of the integrated circuit; and turning-on the first transistor upon receipt of the ESD pulse of the first polarity, turning-on the first transistor comprising capacitively coupling the ESD pulse of the first polarity from the input pad of the integrated circuit to the gate terminal of the first transistor. - View Dependent Claims (22, 23, 24)
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Specification