DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

• US 20170117344A1
• Filed: 10/20/2016
• Published: 04/27/2017
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: YANG, Heejung, KIM, Hyungtae, JANG, Dongun, KIM, Dongsun, HO, Wonjoon
• Granted Patent: US 10,475,872 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2320/0295 by monitoring each display pixel
• CPC Class Codes: G09G 2320/0693 Calibration of display systems
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 2102/341 Short-circuit prevention
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/351 comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Abstract

Provided are a display device and a method of manufacturing the same. A display device includes: a light blocking layer on a first substrate, a buffer layer on the light blocking layer, a semiconductor layer on the buffer layer, an insulating layer on the semiconductor layer, and a source/drain metal layer positioned on the insulating layer, the source/drain metal layer including a non-overlap region that does not overlap the light blocking layer.

Claims

1. A display device, comprising:

a light blocking layer on a first substrate;

a buffer layer on the light blocking layer;

a semiconductor layer on the buffer layer;

an insulating layer on the semiconductor layer; and

a source/drain metal layer positioned on the insulating layer, the source/drain metal layer comprising a non-overlap region that does not overlap the light blocking layer.

2. The display device of claim 1, wherein the non-overlap region has a size greater than or equal to a size of a region in which the semiconductor layer and the source/drain metal layer are electrically connected.

3. The display device of claim 1, wherein the non-overlap region:

is at an outer edge of one surface of an upper end of the light blocking layer; and

has a quadrangular shape.

4. The display device of claim 1, wherein the non-overlap region:

is on an outer edge of a side surface of an upper end of the light blocking layer; and

has a quadrangular shape.

5. The display device of claim 1, wherein the non-overlap region is in a region adjacent to an insulated gate metal layer on the semiconductor layer.

6. The display device of claim 1, wherein a dummy metal layer is between the semiconductor layer and the insulating layer.

7. The display device of claim 6, wherein at least one of the light blocking layer, the gate metal layer, and the source/drain metal layer comprises multiple layers comprising a low reflectivity layer.

8. A method of manufacturing a display device, the method comprising:

providing a light blocking layer on a first substrate;

providing a buffer layer on the light blocking layer;

providing a semiconductor layer on the buffer layer;

providing an insulating layer on the semiconductor layer; and

providing a source/drain metal layer on the insulating layer,

wherein the light blocking layer comprises a non-overlap region in which a portion in which the light blocking layer and the source/drain metal layer overlap is removed.

9. The method of claim 8, wherein the non-overlap region has a size greater than or equal to a size of a region in which the semiconductor layer and the source/drain metal layer are electrically connected.

10. The method of claim 8, wherein the non-overlap region is provided in a region adjacent to an insulated gate metal layer on the semiconductor layer.

11. The method of claim 8, wherein a dummy metal layer is provided between the semiconductor layer and the insulating layer.

12. The method of claim 11, wherein providing at least one of the light blocking layer, the gate metal layer, and the source/drain metal layer comprises providing multiple layers comprising a low reflectivity layer.