ARRAY SUBSTRATE

• US 20170124972A1
• Filed: 07/27/2016
• Published: 05/04/2017
• Est. Priority Date: 10/30/2015
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: YU, SangHee, KIM, Byoungwoo
• Granted Patent: US 10,176,774 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0434 Flat panel display in which a field is applied parallel to the display plane
• CPC Class Codes: G09G 2300/0465 Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.

Claims

1. An array substrate comprising:

a display area;

a non-display area outside of the display area;

a gate-in-panel (GIP) circuit in the non-display area;

a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and

connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit,

wherein each of the plurality of clock signal lines is a ring shaped line.

2. The array substrate of claim 1, wherein the plurality of clock signal lines comprises a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, each having four sides, and

wherein the fourth clock signal line substantially surrounds the third clock signal line, the third clock signal line substantially surrounds the second clock signal line, and the second clock signal line substantially surrounds the first clock signal line.

3. The array substrate of claim 2, wherein the plurality of clock signal lines further comprise:

a fifth clock signal line on at least one side of a respective one of the first to fourth clock signal lines;

a sixth clock signal line on at least one side of a respective one of the first to fourth clock signal lines;

a seventh clock signal line on at least one side of a respective one of the first to fourth clock signal lines; and

an eighth clock signal line on at least one side of a respective one of the first to fourth clock signal lines.

4. The array substrate of claim 3, wherein each of the first to fourth clock signal lines is connected to each of the fifth to eighth clock signal lines, respectively, via at least two contact holes.

5. The array substrate of claim 4, wherein the fifth to eighth clock signal lines are configured to work as external signal input lines.

6. The array substrate of claim 2, wherein each of the first to fourth clock signal lines comprises an auxiliary clock signal line connected to the ring shaped line.

7. The array substrate of claim 2, wherein the first to fourth clock signal lines are formed in the same layer or cross-sectional level and made of the same material as that of at least one among a gate electrode, source and drain electrodes, and a third conductive layer disposed in a layer different from a layer in which the source and drain electrodes are disposed.

8. The array substrate of claim 3, wherein the fifth to eighth clock signal lines are formed in the same layer or cross-sectional level and made of the same material as that of one among a gate electrode, source and drain electrodes, and a third conductive layer disposed in a layer different from a layer in which the source and drain electrodes are disposed.

9. The array substrate of claim 1, wherein the connection lines are configured to connect the plurality of clock signal lines to the GIP circuit via contact holes disposed on the plurality of clock signal lines.

10. An array substrate comprising:

a display area;

a non-display area outside of the display area;

a gate-in-panel (GIP) circuit in the non-display area;

a first clock signal line set in the non-display area and configured to input signals to the GIP circuit;

a second clock signal line set in the non-display area and configured to transfer signals to the GIP circuit; and

first connection lines in the non-display area and configured to connect the first clock signal line set and the second clock signal line set to the GIP circuit,

wherein each of the first clock signal line set and the second clock signal line set comprises first to fourth clock signal lines, respectively, and

each of the first to fourth clock signal lines of the first clock signal line set is connected to each of the first to fourth clock signal lines of the second clock signal line set via second connection lines.

11. The array substrate of claim 10, wherein the first clock signal line set is adjacent to the second clock signal line set in a horizontal or row direction.

12. The array substrate of claim 11, wherein the second connection lines connect each of the first to fourth clock signal lines of the first clock signal line set to each of the first to fourth clock signal lines of the second clock signal line set via contact holes formed on the first to fourth clock signal lines of the first clock signal line set and via contact holes formed on the first to fourth clock signal lines of the second clock signal line set.

13. The array substrate of claim 12, wherein each of the first clock signal line set and the second clock signal line set further comprises:

fifth to eighth clock signal lines on the first to fourth clock signal lines of one of the first clock signal line set and the second clock signal line set, wherein the fifth to eighth clock signal lines are connected to the first to fourth clock signal lines of one of the first or second clock signal line set via contact holes formed on the first to fourth clock signal lines.

14. The array substrate of claim 13, wherein the fifth to eighth clock signal lines are in the same layer and formed of the same material as that of the first connection lines.

15. The array substrate of claim 10, wherein the second connection lines comprise at least two lines.

16. The array substrate of claim 10, wherein the first connection lines and the second connection lines are in the same layer or cross-sectional level, and formed of the same material.

17. An array substrate comprising:

a gate-in-panel (GIP) circuit;

a plurality of clock signal lines configured to transfer signals to the GIP circuit; and

connection lines configured to connect the GIP circuit to the plurality of clock signal lines,

wherein an overlapping area of the connection lines and the plurality of clock signal lines are configured to be minimized so as to reduce RC delay and implement a narrow bezel.

18. The array substrate of claim 17, wherein each of the plurality of clock signal lines has a ring shaped line with four sides.

19. The array substrate of claim 17, wherein each of the plurality of clock signal lines further comprises an auxiliary clock signal line configured to be connected to the respective clock signal lines via a contact hole thereabove.

20. The array substrate of claim 17, wherein some of the plurality of clock signal lines that transfer the same signal to the GIP circuit are connected to one another via the connection lines.

21. A gate-in-panel (GIP) circuit for a display device configured to receive clock signals for sequential operation by a shift register, the GIP circuit comprising:

a structure configured to carry clock signals that reduces a load on the clock signal lines by suppressing a resistance component and a capacitance component of an RC delay, and that reduces overlap capacitance between adjacent lines to implement a narrow bezel.

22. The GIP circuit of claim 21, wherein the structure comprises clock signal lines arranged in concentric square rings.

23. The GIP circuit of claim 22, wherein a part of the structure comprises clock signal lines arranged in multiple cross sectional levels.

24. The GIP circuit of claim 21, wherein a connection line connecting the clock signal lines with each other is formed of a material different from a material of the clock signal lines.

25. The GIP circuit of claim 24, wherein a part of the structure comprises clock signal lines arranged in multiple cross sectional levels.