SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20170141217A1
• Filed: 01/30/2017
• Published: 05/18/2017
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: SHIRAKAWA, Tohru, TAKAHASHI, Hidenori
• Granted Patent: US 10,297,682 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device includes one or more trench gates extending in a first direction in plan view, one or more first-conductivity-type regions spaced away from each other in the first direction, where the first-conductivity-type regions are shallower than the trench gates, one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, where the second-conductivity-type regions are shallower than the trench gates and deeper than the first-conductivity-type regions, and a second-conductivity-type trench spacer region spaced away from the one or more trench gates, where the trench spacer region has a higher concentration than the second-conductivity-type regions. Here, the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

Claims

1. A semiconductor device comprising:

one or more trench gates extending in a first direction in plan view;

one or more first-conductivity-type regions spaced away from each other in the first direction, the first-conductivity-type regions being shallower than the trench gates;

one or more second-conductivity-type regions alternating with the first-conductivity-type regions in the first direction, the second-conductivity-type regions being shallower than the trench gates and deeper than the first-conductivity-type regions; and

a second-conductivity-type trench spacer region spaced away from the one or more trench gates, the trench spacer region having a higher concentration than the second-conductivity-type regions, wherein

the trench spacer region is positioned within the first-conductivity-type regions in plan view and closer to a back surface of the semiconductor device than the first-conductivity-type regions are.

2. The semiconductor device as set forth in claim 1, wherein

a depth of the trench spacer region is equal to or less than half intervals between the one or more trench gates.

3. The semiconductor device as set forth in claim 1, wherein

the trench gates are arranged at a pitch of less than 5 μ

m.

4. The semiconductor device as set forth in claim 3, wherein

the trench gates are arranged at a pitch of 2.4 μ

m or less.

5. The semiconductor device as set forth in claim 1, further comprising:

an insulating film formed on a front surface of the one or more first-conductivity-type regions and having a contact opening therein that penetrates therethrough to reach the one or more first-conductivity-type regions; and

a contact diffusion region formed in the contact opening and connected to the one or more first-conductivity-type regions, wherein

in plan view, a portion of the trench spacer region that overlaps a given one of the first-conductivity-type regions is positioned within the contact opening.

6. The semiconductor device as set forth in claim 5, wherein

in plan view, an impurity concentration in a portion of the given first-conductivity-type region that is positioned within the contact opening is lower than an impurity concentration in a portion of the given first-conductivity-type region that abuts a corresponding one of the trench gates.

7. The semiconductor device as set forth in claim 1, wherein

a portion of the trench spacer region that overlaps a given one of the first-conductivity-type regions in plan view is connected to a portion of the trench spacer region that overlaps a second-conductivity-type region adjacent to the given first-conductivity-type region in plan view.

8. The semiconductor device as set forth in claim 1, wherein

a depth of a portion of the trench spacer region that overlaps a given one of the first-conductivity-type regions in plan view is shallower than a depth of a portion of the trench spacer region that overlaps a second-conductivity-type region adjacent to the given first-conductivity-type region in plan view.

9. The semiconductor device as set forth in claim 1, wherein

a portion of the trench spacer region that overlaps a given one of the first-conductivity-type regions in plan view has a thickness of 0.1 μ

m or less.

10. The semiconductor device as set forth in claim 1, wherein

the first-conductivity-type regions each have a width of 1.4 μ

m or less in the first direction.

11. A manufacturing method for a semiconductor device including a trench gate extending in a first direction in plan view and a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternating with each other in the first direction, the manufacturing method comprising:

forming a plurality of first-conductivity-type regions so as to be spaced away from each other in the first direction;

implanting ions into the plurality of first-conductivity-type regions; and

forming a trench spacer region of a second conductivity type so as to be spaced away from the trench gate, wherein

the trench spacer region overlaps a given one of the plurality of first-conductivity-type regions in plan view and is positioned closer to a back surface of the semiconductor device than the given first-conductivity-type region is.

12. The manufacturing method as set forth in claim 11, wherein

the implantation of the ions into the plurality of first-conductivity-type regions includes:

forming a contact opening above a given one of the plurality of first-conductivity-type regions; and

implanting ions into the contact opening to realize the second conductivity type.

13. The manufacturing method as set forth in claim 12, wherein

the formation of the contact opening above the given first-conductivity-type region includes

applying a contact resist, and

the implantation of the ions into the contact opening to realize the second conductivity type includes

implanting ions through the contact resist.

14. The manufacturing method as set forth in claim 13, wherein

the formation of the contact opening above the given first-conductivity-type region includes

forming an interlayer insulating film on the plurality of first-conductivity-type regions, and

the implantation of the ions into the contact opening to realize the second conductivity type includes

implanting ions through the interlayer insulating film formed on the plurality of first-conductivity-type regions.

15. The manufacturing method as set forth in claim 11, wherein

prior to the

formation of the trench spacer region, the plurality of first-conductivity-type regions are formed.