ACTIVE-BY-ACTIVE PROGRAMMABLE DEVICE

• US 20170220509A1
• Filed: 02/02/2016
• Published: 08/03/2017
• Est. Priority Date: 02/02/2016
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Maidee, Pongstorn, Bolsens, Ivo, Kaviani, Alireza S.
• Granted Patent: US 10,002,100 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

Claims

1. An integrated circuit (IC) system, comprising:

a package substrate having a programmable integrated circuit (IC) die and a companion IC die mounted thereon, the programmable IC die including a programmable fabric and the companion IC die including application circuitry;

a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC die, a second SiP IO circuit disposed in the companion IC die, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit;

first aggregation and first dispersal circuits in the programmable IC die coupled between the programmable fabric and the first SiP IO circuit; and

second aggregation and second dispersal circuits in the companion IC die coupled between the application IO and the second SiP IO circuit.

2. The IC system of claim 1, wherein the first and second SiP IO circuits are configured to:

multiplex multi-channel output of the first and second aggregation circuits, respectively, onto a first plurality of physical channels implemented over the conductive interconnect; and

de-multiplex input from a second plurality of channels implemented over the conductive interconnect onto multi-channel input of the first and second dispersal circuits, respectively.

3. The IC system of claim 1, wherein the first aggregation and the first dispersal circuits comprise a system level interconnect coupled between programmable interconnect of the programmable fabric and the SiP IO circuit.

4. The IC system of claim 3, wherein the system-level interconnect comprises a network-on-chip (NoC).

5. The IC system of claim 1, wherein the programmable IC die comprises a direct connection to the companion IC die separate from the SiP bridge.

6. The IC system of claim 1, wherein the programmable IC die includes arbitration logic, and wherein the first SiP IO circuit comprises a data link circuit and a transceiver circuit, where:

an internal interface of the data link circuit is coupled to the first aggregation and the first dispersal circuits;

an external interface of the data link circuit is coupled to an internal interface of the transceiver circuit;

an external interface of the transceiver circuit is coupled to the conductive interconnect; and

a control interface of the data link circuit is coupled to the arbitration logic.

7. The IC system of claim 6, wherein the arbitration logic is implemented within the programmable fabric of the programmable IC die.

8. The IC system of claim 1, wherein the programmable IC die includes transport logic configured to packetize data transmitted to the first aggregation circuit and de-packetize data received from the first dispersal circuit.

9. The IC system of claim 8, wherein the transport logic is implemented within the programmable fabric of the programmable IC die.

10. A programmable integrated circuit (IC), comprising:

a system-in-package (SiP) input/output (IO) circuit configured to be coupled to a companion IC through external conductive interconnect;

a programmable fabric without at least a portion of application circuitry; and

aggregation and dispersal circuits coupled between the programmable fabric and the SiP IO circuit.

11. The programmable IC of claim 10, wherein the aggregation and the dispersal circuits comprise a system-level interconnect coupled between programmable interconnect of the programmable fabric and the SiP IO circuit.

12. The programmable IC of claim 11, wherein the system-level interconnect comprises a network-on-chip (NoC).

13. The programmable IC of claim 10, wherein the programmable fabric is directly connected to the companion IC separate from the SiP IO circuit.

14. The programmable IC of claim 10, wherein the programmable fabric is configured to implement arbitration logic, and wherein the SiP IO circuit comprises a data link circuit and a transceiver circuit, where:

an internal interface of the data link circuit is coupled to the aggregation and the dispersal circuits;

an external interface of the data link circuit is coupled to an internal interface of the transceiver circuit;

an external interface of the transceiver circuit is coupled to the external conductive interconnect; and

a control interface of the data link circuit is coupled to the arbitration logic.

15. The programmable IC of claim 10, wherein the programmable fabric is configured to implement transport logic that packetizes data transmitted to the aggregation circuit and de-packetizes data received from the dispersal circuit.

16. A method of transmitting data from a programmable integrated circuit (IC) in an IC system, the method comprising:

coupling the data to a first system-in-package (SiP) IO circuit through a plurality of channels of an aggregation circuit in the programmable IC;

transmitting the data from the plurality of channels over a smaller number of physical channels between the programmable IC and a companion IC;

receiving the data from the plurality of physical channels at a second SiP IO circuit in the companion IC; and

coupling the data from the second SiP IO circuit to application circuitry in the companion IC through a plurality of channels of a dispersal circuit in the companion IC.

17. The method of claim 16, wherein the data is divided into packets.

18. The method of claim 17, wherein the second SiP IO circuit includes a plurality of internal output ports coupled to the respective plurality of channels of the dispersal circuit, and wherein the packets each have a destination port selected from one of the plurality of internal output ports.

19. The method of claim 18, wherein the step of transmitting comprises:

queuing the data from the plurality of channels of the aggregation circuit in a respective plurality of transmit queues; and

multiplexing output of the transmit queues among the plurality of physical channels such that packets transmitted in parallel over the plurality of physical channels have different destination ports.

20. The method of claim 19, wherein the step of multiplexing further comprises:

assigning weights to each of the plurality of transmit queues; and

selecting packets from the transmit queues for transmission over the plurality of physical channels based on the weights.