NON-VOLATILE FERROELECTRIC MEMORY CELLS WITH MULTILEVEL OPERATION

• US 20170249983A1
• Filed: 06/03/2015
• Published: 08/31/2017
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: SABIC Global Technologies BV (Government of Saudi Arabia)
• Original Assignee: SABIC Global Technologies BV (Government of Saudi Arabia), Mohd A. Khan
• Inventors: Park, Ji Hoon, Alshareef, Husam N., Khan, Mohd A., Odeh, Ihab N.
• Granted Patent: US 10,068,630 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: G11C 11/2273 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/2275 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/2277 Verifying circuits or methods
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: H10B 53/40 characterised by the peripheral circuit region
• CPC Class Codes: H10N 39/00 Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

Abstract

Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.

Claims

1. A method for storing multiple bits of information in a multi-level ferroelectric memory cell, comprising:

a) receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer;

b) selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and

c) applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern,

wherein the ferroelectric multi-level memory cell is comprised of a ferroelectric capacitor or ferroelectric diode.

2. The method of claim 1, in which the ferroelectric multi-level memory cell comprises the ferroelectric capacitor, and in which the step of applying the at least one write pulse to the memory cell comprises applying the at least one write pulse to the ferroelectric capacitor.

4. The method of claim 1, in which the ferroelectric multi-level memory cell comprises the ferroelectric diode, and in which the step of applying the at least one write pulse to the memory cell comprises applying the at least one write pulse to the ferroelectric diode.

5. The method of claim 4, in which the step of applying the at least one write pulse to the memory cell to create the remnant polarization within the ferroelectric layer comprises modifying a channel resistance between an upper and a lower electrode in the ferroelectric diode, wherein the channel resistance between the upper and the lower electrode is representative of the received bit pattern.

6. The method of claim 1, in which the step of applying the at least one write pulse to the memory cell comprises applying a plurality of write pulses to the memory cell at a frequency based, at least in part, on the received bit pattern.

7. The method of claim 1, further comprising:

sensing a channel resistance of a second multi-level memory cell having a ferroelectric layer; and

determining a second bit pattern stored in the second multi-level memory cell based, at least in part, on the sensed resistance.

8. The method of claim 7, wherein the sensed resistance of the second multi-level memory cell is representative of the remnant polarization of the ferroelectric layer.

9. The method of claim 8, wherein the second multi-level memory cell is the first multi-level memory cell, and the method further comprises verifying the determined second bit pattern is the received bit pattern.

3. (canceled)

10. (canceled)

14. (canceled)

19. (canceled)

20. An apparatus, comprising:

a) a memory cell comprising a ferroelectric capacitor or ferroelectric diode comprising;

an upper electrode;

a lower electrode;

a blend of ferroelectric and semiconducting material between lower and upper electrode; and

b) a controller coupled to the memory cell and configured to perform the steps of;

i. receiving a bit pattern for writing to the memory cell;

ii. selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and

iii. applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.

11. The apparatus of claim 20, in which the controller is configured to create a conduction path in the channel by applying the at least one write pulse to the memory cell based, at least in part, on the pulse duration of the at least one write pulse.

12. The apparatus of claim 20, in which the controller is configured to set a charge carrier level in the conduction channel by applying the at least one write pulse to the memory cell based, at least in part, on the pulse duration of the at least one write pulse.

13. The apparatus of claim 20, in which the controller is configured to receive at least two bits in the received bit pattern.

15. The apparatus of claim 20, in which the ferroelectric layer comprises an organic ferroelectric.

16. The apparatus of claim 20, in which the memory cell is one memory cell of an array of memory cells.

17. The apparatus of claim 20, wherein the controller is further configured to perform the steps of:

i.) detecting a current through the memory cell; and

ii.) determining a bit pattern representative of the detected current.

18. The apparatus of claim 17, wherein the controller is configured to verify the determined bit pattern is equal to the received bit pattern.