FABRICATION OF COMPOUND SEMICONDUCTOR STRUCTURES

• US 20170345654A1
• Filed: 05/27/2016
• Published: 11/30/2017
• Est. Priority Date: 05/27/2016
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Caimi, Daniele, Czornomaz, Lukas, Fompeyrine, Jean, Uccelli, Emanuele
• Granted Patent: US 10,249,492 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02455 Group 13/15 materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02645 Seed materials

Abstract

A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Claims

1. A method for fabricating a compound semiconductor structure, the method comprising:

providing a semiconductor substrate comprising a first semiconductor material;

forming an insulating layer on the semiconductor substrate;

forming an opening in the insulating layer, thereby exposing a seed surface of the substrate, the opening having sidewalls and a bottom, wherein the bottom corresponds to the seed surface of the substrate;

forming a cavity structure above the insulating layer, the cavity structure comprising the opening and a lateral growth channel extending laterally over the substrate;

growing a matching array on the seed surface of the substrate, the matching array comprising at least a first matching structure comprising a second semiconductor material and a second matching structure comprising a third semiconductor material;

growing the compound semiconductor structure comprising a fourth semiconductor material on a seed surface of the matching array;

wherein the first, the second, the third and the fourth semiconductor material are different from each other.

2. The method as claimed in claim 1, wherein the first and the second matching structure are adapted to solve a growth mismatch between the first and the fourth semiconductor material in a stepwise approach.

3. The method as claimed in claim 1, wherein

the first matching structure provides a first matching level between the first and the second semiconductor material;

the second matching structure provides a second matching level between the second semiconductor material and the third semiconductor material; and

the compound semiconductor structure provides a third matching level between the third semiconductor material and the fourth semiconductor material;

wherein the first, the second and the third matching level address a plurality of matching parameters in a sequential way.

4. The method as claimed in claim 3, wherein the third matching level is higher than the second matching level and the second matching level is higher than the first matching level.

5. The method as claimed in claim 3, wherein the first, the second and the third matching level comprise as first matching parameter a lattice match of the lattice constant, as second matching parameter a structural match of the crystal structure and as third matching parameter a chemical similarity match.

6. The method as claimed in claim 5, wherein the first, the second and the third matching level provide an improved match in at least one of the three matching parameters.

7. The method as claimed in claim 5, wherein

the first matching level provides a match in one of the three matching parameters;

the second matching level provides a match in two of the three matching parameters; and

the third matching level provides a match in three of the three matching parameters.

8. The method as claimed in claim 1, wherein

the first matching structure is essentially lattice matched to the semiconductor substrate, but structurally different to the semiconductor substrate;

the second matching structure is structurally matched to the first matching structure, but lattice mismatched to the first matching structure; and

the compound semiconductor structure is lattice matched and structurally matched to the second matching structure.

9. The method as claimed in claim 1, wherein the first semiconductor material is an elementary material.

10. The method as claimed in claim 1, wherein the second and the third second semiconductor material are binary materials and wherein the third semiconductor material is a ternary material.

11. The method as claimed in claim 1, wherein

the semiconductor substrate has a diamond crystal structure;

and

the first matching structure, the second matching structure and the compound semiconductor structure have a zinc blende crystal structure.

12. The method as claimed in claim 1, wherein

the first semiconductor material is a group IV material;

and

the second, third and fourth semiconductor materials are group III-V compound materials or group II-VI compound materials.

13. The method as claimed in claim 1, wherein

the first second semiconductor material is silicon;

the fourth semiconductor material is InGaAs;

the second and third semiconductor materials are selected from the pairs consisting of;

(GaP, InP);

(Ge, GaAs) and (GaSb, GaAsSb).

14. The method as claimed in claim 1, further comprising:

growing the first matching structure in the opening;

growing the second matching structure at least partially in the lateral growth channel.

15. The method as claimed in claim 1, wherein the growing of the first matching structure, the second matching structure and the compound semiconductor structure is performed by one of:

metal organic chemical vapor deposition (MOCVD);

atmospheric pressure CVD;

low or reduced pressure CVD;

ultra-high vacuum CVD;

molecular beam epitaxy (MBE);

atomic layer deposition (ALD) and hydride vapor phase epitaxy.

16. The method as claimed in claim 1, wherein forming the cavity comprises:

forming a sacrificial structure in the opening and on the insulating layer;

forming a cavity layer on the sacrificial structure;

forming an inlet in the cavity layer, thereby exposing a surface of the sacrificial structure;

selectively removing the sacrificial structure, thereby exposing the seed surface of the substrate.

17. The method as claimed in claim 1, wherein the opening of the insulating layer is connected to two or more lateral growth channels extending in different growth directions.

18. The method as claimed in claim 1, further comprising:

growing sequentially in the growth channel in an alternating way one or more first compound semiconductor structures of the fourth semiconductor material and one or more second compound semiconductor structures of a fifth semiconductor material, the fourth semiconductor material being different from the fifth semiconductor material, wherein the first compound semiconductor structures provide a seed surface for the second compound semiconductor structures and the second compound semiconductor structures provide a seed surface for the first compound semiconductor structures;

selectively etching the first or the second compound semiconductor structures, thereby forming a fin structure comprising a plurality of parallel fins of the first or the second compound semiconductor structures.

19. The method as claimed in claim 1, wherein the width of the first and the second compound semiconductor structures in the growth direction is controlled via the time of the epitaxial growth.

20. The method as claimed in claim 1, further comprising providing a geometrical constraint in the growth channel to reduce in plane crystalline defects.

21. The method as claimed in claim 1, wherein the geometrical constraint is an in plane necking of the growth channel.

22. The method as claimed in claim 1, wherein the geometrical constraint is a change of the in plane direction of the growth channel.

23. A compound semiconductor structure obtainable by a method as claimed in claim 1.

24. A wafer comprising a plurality of semiconductor structures as claimed in claim 23.

25. A compound semiconductor structure comprising:

a semiconductor substrate comprising a first semiconductor material;

an insulating layer on the semiconductor substrate;

an opening in the insulating layer, the opening having sidewalls and a bottom, wherein the bottom corresponds to a seed surface of the substrate;

a cavity structure above the insulating layer, the cavity structure comprising the opening and a lateral growth channel extending laterally over the substrate;

a matching array epitaxially grown on the seed surface of the substrate, the matching array comprising at least a first matching structure comprising a second semiconductor material and a second matching structure comprising a third semiconductor material;

a compound semiconductor structure comprising a fourth semiconductor material epitaxially grown on a seed surface of the matching array;

wherein the first, the second, the third and the fourth semiconductor material are different from each other.