HIGH PERFORMANCE INTERCONNECT LINK LAYER

• US 20180011759A1
• Filed: 09/15/2017
• Published: 01/11/2018
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Willey, Jeff, Blankenship, Robert G., Swanson, Jeffrey C., Safranek, Robert J.
• Granted Patent: US 10,365,965 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272

Abstract

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

Claims

1-78. -78. (canceled)

79. An apparatus comprising:

a host processor comprising;

physical layer logic; and

link layer logic, wherein the link layer logic is to;

generate a flit comprising a plurality of slots, wherein one or more of the slots is encoded with a return credit response, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet; and

a transmitter to send the flit on a link to another device.

80. The apparatus of claim 79, wherein a single one of the slots is encoded with the return credit response

81. The apparatus of claim 79, wherein the other device comprises another host processor device.

82. The apparatus of claim 79, wherein the link supports a plurality of lane widths.

83. The apparatus of claim 82, wherein the plurality of lane widths comprises a lane width of at least 8 lanes.

84. The apparatus of claim 79, wherein the flit comprises at least 192 bits.

85. The apparatus of claim 79, wherein the physical layer comprises an electrical transmission medium.

86. The apparatus of claim 79, wherein the physical layer comprises an optical transmission medium.

87. An apparatus comprising:

a host processor comprising;

a receiver to receive a flit from another device over a link, wherein the flit comprises a plurality of slots, one or more of the slots is encoded with a return credit response, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet;

a protocol stack comprising physical layer logic and link layer logic, wherein the link layer logic is to return a number of credits to a credit pool based on the return credit response.

88. The apparatus of claim 87, wherein the credit pool corresponds to a virtual channel of the link.

89. The apparatus of claim 87, wherein a single one of the slots is encoded with the return credit response

90. The apparatus of claim 87, wherein the other device comprises another host processor device.

91. The apparatus of claim 87, wherein the link supports a plurality of lane widths.

92. The apparatus of claim 91, wherein the plurality of lane widths comprises a lane width of at least 8 lanes.

93. The apparatus of claim 87, wherein the flit comprises at least 192 bits.

94. The apparatus of claim 87, wherein the physical layer comprises an electrical transmission medium.

95. The apparatus of claim 87, wherein the physical layer comprises an optical transmission medium.

96. A system comprising:

a first host processor device;

a second host processor device to connect to the first host processor device using a link, wherein the second host processor device comprises;

physical layer logic; and

link layer logic, wherein the link layer logic is to;

generate a flit comprising a plurality of slots, wherein one or more of the slots is encoded with a return credit response, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet; and

a transmitter to send the flit on a link to another device.

97. The system of claim 96, wherein a single one of the slots is encoded with the return credit response

98. The system of claim 96, wherein the other device comprises another host processor device.

99. The system of claim 96, wherein the link supports a plurality of lane widths.

100. The system of claim 99, wherein the plurality of lane widths comprises a lane width of at least 8 lanes.

101. The system of claim 96, wherein the flit comprises at least 192 bits.

102. The system of claim 96, wherein the physical layer comprises an electrical transmission medium.

103. The system of claim 96, wherein the physical layer comprises an optical transmission medium.

104. A system comprising:

means for generating a flit comprising a plurality of slots, wherein one or more of the slots is encoded with a return credit response, the flit is according to a format to enable a plurality of transaction headers to be contained in the flit, and the flit comprises a piece of a larger network packet; and

means for sending the flit on a link to another device.