CONFIGURABLE LOGIC PLATFORM WITH MULTIPLE RECONFIGURABLE REGIONS

• US 20180089119A1
• Filed: 09/29/2016
• Published: 03/29/2018
• Est. Priority Date: 09/29/2016
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Khan, Asif, Atta, Islam Mohamed Hatem Abdulfattah Mohamed, Johnson, Robert Michael, Davis, Mark Bradley, Pettey, Christopher Joseph, Bshara, Nafea, Izenberg, Erez
• Granted Patent: US 10,282,330 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Claims

1. A configurable logic platform comprising:

a physical interconnect for connecting the configurable logic platform to a processor;

a first reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the first reconfigurable logic region;

a second reconfigurable logic region comprising logic blocks that are configured based on configuration data corresponding to the second reconfigurable logic region;

a configuration port for applying the configuration data to the first and second reconfigurable logic regions so that the first reconfigurable logic region is configured based on the configuration data corresponding to the first reconfigurable logic region and the second reconfigurable logic region is configured based on the configuration data corresponding to the second reconfigurable logic region;

a control plane function accessible via transactions of the physical interconnect, the control plane function in communication with the configuration port, the control plane function providing restricted access to the configuration port from the physical interconnect;

a first data plane function accessible via transactions of the physical interconnect, the first data plane function providing an interface to the first reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the first reconfigurable logic region from directly accessing the physical interconnect;

a second data plane function accessible via transactions of the physical interconnect, the second data plane function providing an interface to the second reconfigurable logic region which allows information to be transmitted over the physical interconnect and prevents the second reconfigurable logic region from directly accessing the physical interconnect; and

arbitration logic configured to apportion bandwidth of the physical interconnect among at least the first data plane function and the second data plane function.

2. The configurable logic platform of claim 1, wherein the first data plane function is accessed using a transaction comprising an address within a first address range, the second data plane function is accessed using a transaction comprising an address within a second address range, the control plane function is accessed using a transaction comprising an address within a third address range, and the first, second, and third address ranges are all non-overlapping.

3. The configurable logic platform of claim 1, further comprising:

a public peripheral interface configured to provide a first communication path between the first reconfigurable logic region and a public peripheral and a second communication path between the second reconfigurable logic region and a public peripheral.

4. The configurable logic platform of claim 3, wherein the public peripheral interface is configured to restrict access by the first reconfigurable logic region to addresses of the public peripheral within a first address range, and the public peripheral interface is configured to restrict access by the second reconfigurable logic region to addresses of the public peripheral within a second address range.

5. The configurable logic platform of claim 3, wherein the public peripheral interface is configured to restrict the first reconfigurable logic region to a first amount of bandwidth for transfers between the public peripheral and the first reconfigurable logic region, and the public peripheral interface is configured to restrict the second reconfigurable logic region to a second amount of bandwidth for transfers between the public peripheral and the second reconfigurable logic region.

6. An apparatus comprising:

a plurality of reconfigurable logic regions, each reconfigurable logic region comprising configurable hardware to implement a respective application logic design; and

host logic for separately encapsulating each of the reconfigurable logic regions, the host logic comprising;

a host interface for communicating with a processor; and

a plurality of data path functions accessible via the host interface, each data path function comprising a layer for formatting data transfers between the host interface and the application logic design of a corresponding reconfigurable logic region, and wherein the host interface is configured to arbitrate between resources of the application logic designs of the respective reconfigurable logic regions.

7. The apparatus of claim 6, wherein the host logic further comprises:

a management function accessible via the host interface, the management function adapted to cause a reconfigurable logic region of the plurality of reconfigurable logic regions to be configured with a particular application logic design in response to an authorized transaction received at the host interface.

8. The apparatus of claim 6, wherein the host interface is further configured to enforce a maximum transfer size of the application logic of the respective reconfigurable logic regions.

9. The apparatus of claim 6, wherein the management function and each of the data path functions are accessible using different non-overlapping address ranges for each of the respective functions.

10. The apparatus of claim 6, wherein the host interface apportions bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions based on a programmed value of a control register of the host logic.

11. The apparatus of claim 6, wherein at least a portion of the host logic is reconfigurable logic that is loaded on the apparatus in response to an authorized transaction received at the host interface.

12. The apparatus of claim 6, wherein the host logic further comprises a translation layer between the application logic of the respective reconfigurable logic regions and a public peripheral, the translation layer adapted to format data transfers between the application logic and logic the public peripheral.

13. The apparatus of claim 12, wherein the host logic further comprises logic for apportioning bandwidth of data transfers between the application logic of the different reconfigurable logic regions and the public peripheral.

14. The apparatus of claim 12, wherein the host logic further comprises logic for enforcing access restrictions from the application logic of the different reconfigurable logic regions to the public peripheral.

15. A method for operating a configurable hardware platform comprising reconfigurable logic, the method comprising:

loading host logic on a first region of the reconfigurable logic so that the configurable hardware platform performs operations of the host logic, the host logic including a host interface and a control plane function enforcing restricted access for transactions from the host interface;

loading a first application logic design on a second region of the reconfigurable logic in response to receiving a first transaction at the host interface, the first transaction satisfying access criteria of the control plane function;

loading a second application logic design on a third region of the reconfigurable logic in response to receiving a second transaction at the host interface, the second transaction satisfying access criteria of the control plane function; and

using the host logic to arbitrate between resources used by each of the first application logic design and the second application logic design when transmitting information from the host interface.

16. The method of claim 15, further comprising:

using the host logic as an interface between a shared peripheral and the first application logic design and the second application logic design.

17. The method of claim 16, further comprising:

using the host logic to apportion bandwidth of data transfers between the shared peripheral and the first application logic design and the second application logic design.

18. The method of claim 16, further comprising:

using the host logic to enforce a size of data transfers between the shared peripheral and the first application logic design and the second application logic design.

19. The method of claim 16, further comprising:

using the host logic to restrict access from the first application logic design to a first range of addresses of the shared peripheral and to restrict access from the second application logic design to a second range of addresses of the shared peripheral.

20. The method of claim 19, further comprising:

clearing one or more of an internal memory, an external memory, or a configuration memory in response to tearing down the first application logic design or the second application logic design.