MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES
First Claim
1. A memory structure, comprising:
- a semiconductor substrate having a substantially planar surface and having circuitry formed therein or thereon;
an insulation layer over the semiconductor substrate;
a first active strip and a second active strip formed over the insulating layer, each extending lengthwise along a second direction with each other and each extending along a first direction substantially parallel to the planar surface and separated from each other by a predetermined distance along a second direction that is also substantially parallel to the planar surface, wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, and wherein the first semiconductor layer of each active strip comprises (i) first and second semiconductor strips of the first conductivity type each extending lengthwise along the first direction on opposite sides of the active strip and (ii) a dielectric material electrically isolating the first and second semiconductor strips from each other;
a charge-trapping material; and
a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being spaced by the charge-trapping material from the first active strip or the second active strip, thereby forming along the first direction, on each side of each active strip, a NOR string, each NOR string including a plurality of storage transistors that are formed out of the first or second semiconductor strip, the second and the third semiconductor layers of the active strip, and the charge-trapping material and the conductors along the side of the active strip.
1 Assignment
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Accused Products
Abstract
Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
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Citations
24 Claims
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1. A memory structure, comprising:
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a semiconductor substrate having a substantially planar surface and having circuitry formed therein or thereon; an insulation layer over the semiconductor substrate; a first active strip and a second active strip formed over the insulating layer, each extending lengthwise along a second direction with each other and each extending along a first direction substantially parallel to the planar surface and separated from each other by a predetermined distance along a second direction that is also substantially parallel to the planar surface, wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, and wherein the first semiconductor layer of each active strip comprises (i) first and second semiconductor strips of the first conductivity type each extending lengthwise along the first direction on opposite sides of the active strip and (ii) a dielectric material electrically isolating the first and second semiconductor strips from each other; a charge-trapping material; and a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being spaced by the charge-trapping material from the first active strip or the second active strip, thereby forming along the first direction, on each side of each active strip, a NOR string, each NOR string including a plurality of storage transistors that are formed out of the first or second semiconductor strip, the second and the third semiconductor layers of the active strip, and the charge-trapping material and the conductors along the side of the active strip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory structure, comprising:
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a semiconductor substrate having a substantially planar surface having circuitry formed in and on the planar surface of the semiconductor substrate; an insulating layer over the semiconductor substrate; a first stack of active strips and a second stack of active strips formed over the insulating layer, wherein each stack of active strips comprises two or more active strips provided one on top of another on isolated planes and being substantially aligned lengthwise with each other along a first direction substantially parallel to the planar surface, wherein the first stack and the second stack being separated from each other a predetermined distance along a second direction transverse the first direction and parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type; a charge-trapping material; a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being separated from the first or the second stack of active strips by the charge-trapping material, thereby forming in each active strip a NOR string, each NOR string including a plurality of storage transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and the adjacent charge-trapping material and conductors; and a first set of global conductive wiring each running along the second direction for connecting the conductors to the circuitry. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification