Radio Frequency Signal Router
First Claim
1. A RF router comprising:
- an input stage comprising a plurality of RF input terminals, wherein each RF input terminal is configured to receive an input RF signal, and wherein each input stage further comprises;
a plurality of input switch matrices;
a plurality of intermediate switch matrices, wherein inputs of each intermediate switch matrices are coupled to outputs of the input switch matrices such that each input of each intermediate switch matrix is coupled to exactly one output of the plurality of input switch matrices; and
an output stage comprising;
a plurality of output switch matrices, wherein inputs of each output switch matrix are coupled to outputs of the intermediate switch matrices such that each input of each output switch matrix is coupled to exactly one output of the plurality of intermediate switch matrices;
wherein at least one of the plurality of input switch matrices, the plurality of intermediate switch matrices and the plurality of output switch matrices are redundant.
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Accused Products
Abstract
A RF router for routing n input signals to m destinations, where the router comprises a backplane coupled to a plurality of RF input terminals, a plurality of RF output terminals, a plurality of splitters and a plurality of connectors. The backplane is also coupled to a controller and a plurality of connectors for receiving a plurality of switching matrices. The RF router comprises a plurality of u×v input switch matrices, a plurality of p×q intermediate switch matrices and a plurality of r×s output switch matrices, where at least one of the plurality of u×v input switch matrices, the plurality of p×q intermediate switch matrices and the plurality of r×s output switch matrices are redundant.
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25 Claims
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1. A RF router comprising:
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an input stage comprising a plurality of RF input terminals, wherein each RF input terminal is configured to receive an input RF signal, and wherein each input stage further comprises; a plurality of input switch matrices; a plurality of intermediate switch matrices, wherein inputs of each intermediate switch matrices are coupled to outputs of the input switch matrices such that each input of each intermediate switch matrix is coupled to exactly one output of the plurality of input switch matrices; and an output stage comprising; a plurality of output switch matrices, wherein inputs of each output switch matrix are coupled to outputs of the intermediate switch matrices such that each input of each output switch matrix is coupled to exactly one output of the plurality of intermediate switch matrices; wherein at least one of the plurality of input switch matrices, the plurality of intermediate switch matrices and the plurality of output switch matrices are redundant. - View Dependent Claims (2, 3, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 19, 20, 21, 22, 23, 24)
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4. (canceled)
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5. (canceled)
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11. (canceled)
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17. (canceled)
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18. (canceled)
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25. (canceled)
Specification