HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER

• US 20180095927A1
• Filed: 11/22/2017
• Published: 04/05/2018
• Est. Priority Date: 10/22/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Iyer, Venkatraman, Jue, Darren S., Shah, Rahul C., Kumar, Arvind A.
• Granted Patent: US 10,216,661 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 13/22 using successive scanning, e.g. polling G06F13/24 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4286 using a handshaking protocol, e.g. RS232C link
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 2212/622 State-only directory, i.e. not recording identity of sharing or owning nodes
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06F 8/73 : Program documentation
• CPC Class Codes: G06F 8/77 : Software metrics
• CPC Class Codes: G06F 9/30145 : Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/44505 : Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/466 : Transaction processing
• CPC Class Codes: H04L 12/4641 : Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 45/74 : Address processing for routing
• CPC Class Codes: H04L 49/15 : Interconnection of switching modules
• CPC Class Codes: H04L 9/0662 : with particular pseudorandom sequence generator
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/00 : Reducing energy consumption in communication networks

Abstract

A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.

Claims

1-50. -50. (canceled)

51. An apparatus comprising:

a receiver processor comprising an agent to support a layered protocol stack comprising physical layer logic, link layer logic, and protocol layer logic, wherein the agent is to;

receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;

intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;

receive a control code within the L0c interval; and

initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.

52. The apparatus of claim 51, wherein the control code mismatch is based on a bit error.

53. The apparatus of claim 51, wherein the physical layer logic is further to attempt to resolve the bit error and the control code mismatch is identified in response to a failure to resolve the bit error.

54. The apparatus of claim 51, wherein the control code is to be from a set comprising a reset request code, a low power entry request, a partial width entry request, and a partial width exit request.

55. The apparatus of claim 51, wherein the L0c interval is to be entered according to a defined interval.

56. The apparatus of claim 55, wherein the L0c interval is to be entered periodically according to the defined interval.

57. The apparatus of claim 51, wherein the L0c interval is a defined length.

58. The apparatus of claim 51, wherein the L0c interval is to begin and end on clean flit boundaries.

59. The apparatus of claim 51, wherein the control code comprises an 8-bit code.

60. The apparatus of claim 51, wherein the control code comprises a request control sequence.

61. The apparatus of claim 51, wherein the agent is further to detect that the control code fails to match one of a set of specified codes.

62. The apparatus of claim 61, wherein the agent comprises comparison circuitry to detect that the control code fails to match one of the set of specified codes.

63. The apparatus of claim 51, further comprising transmitter logic to send data to indicate entry into L0c, and send one or more control codes within L0c intervals.

64. The apparatus of claim 51, wherein the reset comprises an in-band reset.

65. A method comprising:

receiving a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;

intermittently entering a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;

receiving a control code within the L0c interval; and

initiating a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.

66. The method of claim 65, further comprising sending one or more control codes within the L0c interval.

67. The method of claim 65, further comprising detecting that the control code fails to match one of the set of specified codes.

68. A system comprising:

means for receiving a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;

means for intermittently entering a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;

means for receiving a control code within the L0c interval; and

means for initiating a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.

69. A system comprising:

a first computing device; and

a second computing device coupled to the first computing device by a link, wherein the second processor device comprises;

link layer circuitry to receive a link layer data stream within an active link state (L0), wherein the link layer data comprises a set of flits;

state machine logic to intermittently enter a coordination link state (L0c), wherein the coordination link state defines a L0c interval in which physical layer control;

physical layer circuitry to;

identify a control code received from the first computing device within the L0c interval; and

initiate a reset of the link based on a control code mismatch, wherein the control code mismatch is based on an identification that the control code fails to match one of a set of specified codes.

70. The system of claim 69, wherein the first computing device comprises a first processor and the second computing device comprises a second processor.