SEMICONDUCTOR STORAGE DEVICE

• US 20180276070A1
• Filed: 09/08/2017
• Published: 09/27/2018
• Est. Priority Date: 03/21/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: LIN, Wangying, KODERA, Shunsuke
• Granted Patent: US 10,452,474 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

According to an embodiment, a semiconductor storage device includes a detection circuit configured to detect an error in data read from a first memory cell array. The read data of a size corresponding to a page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided. When performing a first operation of concurrently executing outputting of first data read from the first memory cell array to an outside and reading of second data different from the first data from the first memory array, an interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

Claims

1. A semiconductor storage device comprising:

an interface circuit configured to communicate with an outside;

a first memory cell array which includes a memory cell transistor configured to hold data and from which data is read for each page unit; and

a detection circuit configured to detect an error in data read from the first memory cell array,

wherein the read data of a size corresponding to the page unit is subjected to detection of an error for each of a plurality of first units into which the page unit is divided, and

when performing a first operation of concurrently executing outputting of first data read from the first memory cell array to the outside and reading of second data different from the first data from the first memory array, the interface circuit is configured to output information based on the error detected with respect to the first data to the outside.

2. The device of claim 1, wherein the information includes one of an error bit count detected for each of the first units and a value indicating whether the error bit count detected for each of the first units exceeds a given threshold and a maximum value of the error bit count detected for each of the first units.

3. The device of claim 2, wherein the threshold is configured to be set from the outside.

4. The device of claim 2, wherein the threshold includes a fixed value.

5. The device of claim 2, wherein the interface circuit outputs the information concerning the first data to the outside upon receiving a first command in the first operation, and

outputs the information concerning the second data to the outside upon receiving a second command after the first operation.

6. The device of claim 2, further comprising a table configured to hold the information concerning each of the first data and the second data,

wherein the interface circuit outputs the information concerning each of the first data and the second data from the table.

7. The device of claim 6, wherein the interface circuit consecutively outputs the information concerning the first data for each of the first units from the table upon receiving a first command in the first operation.

8. The device of claim 6, wherein the interface circuit outputs, from the table, the error bit count of a portion, of the information concerning the first data, which corresponds to the first unit, upon receiving a first command in the first operation.

9. The device of claim 1, wherein the interface circuit recognizes, as a command, an input signal which is different from an asserted chip select signal and is received immediately after reception of the chip select signal.

10. The device of claim 1, wherein the interface circuit recognizes, as a command, an input signal received during reception of an asserted command latch enable signal.

11. The device of claim 1, further comprising a second memory cell array which includes a memory cell transistor configured to hold data and from which data is read for each page unit,

wherein the error detection circuit further detects an error in data read from the second memory cell array, and

when performing a second operation of concurrently executing outputting of third data read from the second memory cell array to the outside and reading of fourth data different from the third data from the second memory array, the interface circuit is configured to output information based on the error detected with respect to the third data to the outside, and

concurrently execute the first operation and the second operation.

12. The device of claim 11, wherein the information includes one of an error bit count detected for each of the first units and a value indicating whether the error bit count detected for each of the first units exceeds a given threshold and a maximum value of the error bit count detected for each of the first units.

13. The device of claim 12, wherein the threshold is configured to be set from the outside.

14. The device of claim 12, wherein the threshold includes a fixed value.

15. The device of claim 12, wherein the interface circuit outputs the information concerning the first data to the outside upon receiving a first command in the second operation,

outputs the information concerning the second data to the outside upon receiving a second command in the second operation,

outputs the information concerning the third data to the outside upon receiving a third command after the second operation, and

outputs the information concerning the fourth data to the outside upon receiving a fourth command after the second operation.

16. The device of claim 12, further comprising a table configured to hold the information concerning data read from the first memory cell array and the second memory cell array,

wherein the interface circuit outputs the information concerning each of the first data, the second data, the third data, and the fourth data from the table.