SEMICONDUCTOR DEVICE
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Abstract
A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.
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Citations
40 Claims
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1-20. -20. (canceled)
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21. A semiconductor device, comprising:
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a first substrate including a first region and a second region; a first lower interconnection structure on the first region of the first substrate; a second lower interconnection structure on the second region of the first substrate; a second substrate on or above the first lower interconnection structure; a memory cell array on the second substrate; a first vertical contact penetrating through the memory cell array and the second substrate, and contacting the first lower interconnection structure; a second vertical contact contacting the second lower interconnection structure; and a channel layer penetrating through the memory cell array and contacting the second substrate. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A semiconductor device, comprising:
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a first substrate including a first region and a second region; at least one first insulating layer on the first substrate; a first lower interconnection structure in the at least one first insulating layer and on the first region of the first substrate; a second substrate on the at least one first insulating layer, and on or above the first lower interconnection structure; a memory cell array on the second substrate; a first vertical contact penetrating through the memory cell array and the second substrate, and contacting the first lower interconnection structure; and a channel layer penetrating through the memory cell array, and directly contacting an upper surface of the second substrate, wherein the first vertical contact is directly above the first region of the first substrate. - View Dependent Claims (34, 35, 36, 37, 38)
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39. A semiconductor device, comprising:
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a first substrate including a first region and a second region; at least one first insulating layer on the first substrate; a second insulating layer on the at least one first insulating layer; a first lower interconnection structure in the at least one first insulating layer and on the first region of the first substrate; a second lower interconnection structure in the at least one first insulating layer and on the second region of the first substrate; a second substrate on the at least one first insulating layer and on or above the first lower interconnection structure; a memory cell array on the second substrate; a first vertical contact penetrating through the memory cell array and the second substrate, and contacting the first lower interconnection structure; a second vertical contact penetrating through the second insulating layer and contacting the second lower interconnection structure; a channel layer penetrating through the memory cell array, and directly contacting an upper surface of the second substrate; and an upper interconnection layer electrically connected to the first lower interconnection structure via the first vertical contact. - View Dependent Claims (40)
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Specification