CACHE MEMORY SHARED BY SOFTWARE HAVING DIFFERENT TIME-SENSITIVITY CONSTRAINTS

• US 20190324912A1
• Filed: 04/18/2018
• Published: 10/24/2019
• Est. Priority Date: 04/18/2018
• Status: Abandoned Application

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: Toivanen, Jukka
• Application Number:
  US15/956,010
• Publication Number:
  US 20190324912A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/282 Partitioned cache
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping

Abstract

A device including a cache memory that is partitioned into at least a first partition and a second partition. The first partition and the second partition are distinguishable by memory addresses. The first partition is dedicated to a first category of software and the second partition is dedicated to a second category of software. The first category and the second category have different time-sensitivity constraints. The device further includes a processor operative to execute software that includes a first software portion belonging to the first category and a second software portion belonging to the second category.

Claims

1. A device operative to execute software of two or more categories, comprising:

a processor operative to execute the software, the software including a first software portion belonging to a first category and a second software portion belonging to a second category, wherein the first category and the second category have different time-sensitivity constraints;

a cache memory coupled to the processor, the cache memory including at least a first partition and a second partition, the first partition dedicated to the first category and the second partition dedicated to the second category; and

circuitry operative to receive a memory access request specifying a memory address, and determine whether to access the first partition or the second partition by the memory address.

2. The device of claim 1, wherein the first partition is mapped to a first memory address range and the second partition is mapped to a second memory address range.

3. The device of claim 2, wherein the first memory address range and the second memory address range are in a physical memory address space of a memory device.

4. The device of claim 2, wherein the first memory address range is in a physical memory address space of a memory device, and the second memory address range is in an alias memory address space outside the physical memory address space.

5. The device of claim 4, wherein an address area between an ending boundary of the first memory address range and a beginning boundary of the second memory address range has a same size as the physical memory address space.

6. The device of claim 1, further comprising circuitry operative to detect an access type of a memory access according to one address bit of the memory access.

7. The device of claim 1, wherein the cache memory is configurable to operate in one of a partitioned mode and a non-partitioned mode.

8. The device of claim 1, wherein the cache memory is configurable to have different partition sizes.

9. The device of claim 1, wherein the cache memory is configurable to have more than two partitions dedicated to more than two categories of software.

10. The device of claim 1, wherein the cache memory partitioning is configurable at runtime according to the software being executed.

11. A method for operating a cache memory, comprising:

receiving a memory access request specifying a memory address; and

determining whether to access a first partition or a second partition of the cache memory by the memory address, wherein the first partition is dedicated to a first category of software and the second partition is dedicated to a second category of software, and wherein the first category and the second category have different time-sensitivity constraints.

12. The method of claim 11, wherein the first partition is mapped to a first memory address range and the second partition is mapped to a second memory address range.

13. The method of claim 12, wherein the first memory address range and the second memory address range are in a physical memory address space of a memory device.

14. The method of claim 12, wherein the first memory address range is in a physical memory address space of a memory device, and the second memory address range is in an alias memory address space outside the physical memory address space.

15. The method of claim 14, wherein an address area between an ending boundary of the first memory address range and a beginning boundary of the second memory address range has a same size as the physical memory address space.

16. The method of claim 11, further comprising:

detecting an access type of a memory access according to one address bit of the memory access.

17. The method of claim 11, wherein the cache memory is configurable to operate in one of a partitioned mode and a non-partitioned mode.

18. The method of claim 11, wherein the cache memory is configurable to have different partition sizes.

19. The method of claim 11, wherein the cache memory is configurable to have more than two partitions dedicated to more than two categories of software.

20. The method of claim 11, wherein the cache memory partitioning is configurable at runtime according to the software being executed.