CACHE MEMORY SHARED BY SOFTWARE HAVING DIFFERENT TIME-SENSITIVITY CONSTRAINTS
First Claim
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1. A device operative to execute software of two or more categories, comprising:
- a processor operative to execute the software, the software including a first software portion belonging to a first category and a second software portion belonging to a second category, wherein the first category and the second category have different time-sensitivity constraints;
a cache memory coupled to the processor, the cache memory including at least a first partition and a second partition, the first partition dedicated to the first category and the second partition dedicated to the second category; and
circuitry operative to receive a memory access request specifying a memory address, and determine whether to access the first partition or the second partition by the memory address.
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Abstract
A device including a cache memory that is partitioned into at least a first partition and a second partition. The first partition and the second partition are distinguishable by memory addresses. The first partition is dedicated to a first category of software and the second partition is dedicated to a second category of software. The first category and the second category have different time-sensitivity constraints. The device further includes a processor operative to execute software that includes a first software portion belonging to the first category and a second software portion belonging to the second category.
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20 Claims
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1. A device operative to execute software of two or more categories, comprising:
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a processor operative to execute the software, the software including a first software portion belonging to a first category and a second software portion belonging to a second category, wherein the first category and the second category have different time-sensitivity constraints; a cache memory coupled to the processor, the cache memory including at least a first partition and a second partition, the first partition dedicated to the first category and the second partition dedicated to the second category; and circuitry operative to receive a memory access request specifying a memory address, and determine whether to access the first partition or the second partition by the memory address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for operating a cache memory, comprising:
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receiving a memory access request specifying a memory address; and determining whether to access a first partition or a second partition of the cache memory by the memory address, wherein the first partition is dedicated to a first category of software and the second partition is dedicated to a second category of software, and wherein the first category and the second category have different time-sensitivity constraints. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification