Configuring Different Via Sizes for Bridging Risk Reduction and Performance Improvement
First Claim
1. A semiconductor device, comprising:
- a first gate structure, a second gate structure, and a third gate structure that each extend in a first direction;
a first gate via disposed on the first gate structure, the first gate via having a first size;
a second gate via disposed on the second gate structure, the second gate via having a second size that is greater than the first size;
a third gate via disposed on the third gate structure, the third gate via having a third size that is less than the second size but greater than the first size;
a first source contact disposed adjacent to a first side of the first gate via;
a first drain contact disposed adjacent to a second side of the first gate via opposite the first side; and
a second drain contact is disposed adjacent to a first side of the third gate via.
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Accused Products
Abstract
A first gate structure, a second gate structure, and a third gate structure each extend in a first direction. A first gate via is disposed on the first gate structure. The first gate via has a first size. A second gate via is disposed on the second gate structure. The second gate via has a second size that is greater than the first size. A third gate via is disposed on the third gate structure. The third gate via has a third size that is less than the second size but greater than the first size. A first source contact is disposed adjacent to a first side of the first gate via. A first drain contact is disposed adjacent to a second side of the first gate via opposite the first side. A second drain contact is disposed adjacent to a first side of the third gate via.
7 Citations
20 Claims
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1. A semiconductor device, comprising:
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a first gate structure, a second gate structure, and a third gate structure that each extend in a first direction; a first gate via disposed on the first gate structure, the first gate via having a first size; a second gate via disposed on the second gate structure, the second gate via having a second size that is greater than the first size; a third gate via disposed on the third gate structure, the third gate via having a third size that is less than the second size but greater than the first size; a first source contact disposed adjacent to a first side of the first gate via; a first drain contact disposed adjacent to a second side of the first gate via opposite the first side; and a second drain contact is disposed adjacent to a first side of the third gate via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device, comprising:
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a first gate structure, a second gate structure, and a third gate structure that each extend in a first direction; a plurality of fin structures that each extend in a second direction perpendicular to the first direction, wherein the fin structures are each wrapped around by the first gate structure, the second gate structure, and third gate structure; a first gate via disposed on the first gate structure, the first gate via having a first dimension, wherein the first gate via overlap with one of the fin structures in a top view; a second gate via disposed on the second gate structure, the second gate via having a second dimension that is greater than the first dimension, wherein the second gate via does not overlap with any of the fin structures in the top view; and a third gate via disposed on the third gate structure, the third gate via having a third dimension that is less than the second dimension but greater than the first dimension, wherein the second gate via does not overlap with any of the fin structures in the top view; and a plurality of source/drain contacts that each extend in the first direction; wherein; both a first side and a second side of the first gate via have source/drain contacts located adjacent thereto, wherein the first side and the second side are opposite one another in the second direction; neither the first side nor the second side of the second gate via has source/drain contacts located adjacent thereto; and the first side but not the second side of the third gate via has one of the source/drain contacts located adjacent thereto. - View Dependent Claims (11, 12, 13, 14)
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15. A method, comprising:
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receiving an integrated circuit (IC) layout design, wherein the IC layout design includes a first gate via located on a first gate, a second gate via located on a second gate, and a third via located on a third gate, and wherein the first gate via has source/drain contacts located adjacent thereto on both a first side and a second side opposite the first side, the second gate via has no source/drain contacts located adjacent thereto on either the first side or the second side, and the third gate via has a source/drain contact located adjacent to the first side but not the second side; and revising the IC layout design by adjusting a size of at least one of the first gate via, the second gate via, or the third gate via, wherein after the adjusting, the second gate via has a larger size than the third gate via, and the third gate via has a larger size than the first gate via. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification