STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH HYBRID FINS

• US 20200135729A1
• Filed: 12/27/2019
• Published: 04/30/2020
• Est. Priority Date: 05/16/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: NG, Jin-Aun, CHIANG, Kuo-Cheng, CHIANG, Hung-Li, CHEN, Tzu-Chiang, CHEN, I-Sheng
• Granted Patent: US 11,398,476 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device structure also includes a first fin structure over the semiconductor substrate and surrounded by the isolation structure and a stack of nanostructures over the first fin structure. The nanostructures are separated from each other. The semiconductor device structure further includes a second fin structure over the semiconductor substrate. The second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure. The embedded portion is separated from the protruding portion by a distance.

Claims

1. A semiconductor device structure, comprising:

a semiconductor substrate;

an isolation structure over the semiconductor substrate;

a first fin structure over the semiconductor substrate and surrounded by the isolation structure;

a stack of nanostructures over the first fin structure, wherein the nanostructures are separated from each other; and

a second fin structure over the semiconductor substrate, wherein the second fin structure has an embedded portion surrounded by the isolation structure and a protruding portion over the isolation structure, and the embedded portion is separated from the protruding portion by a distance.

2. The semiconductor device structure as claimed in claim 1, wherein a total height of the stack of the nanostructures is greater than a total height of the first fin structure.

3. The semiconductor device structure as claimed in claim 2, wherein a total height of the protruding portion of the second fin structure is greater than a total height of the embedded portion of the second fin structure.

4. The semiconductor device structure as claimed in claim 3, wherein a total height of the protruding portion of the second fin structure is greater than a total height of the stack of the nanostructures.

5. The semiconductor device structure as claimed in claim 1, wherein a total height of the protruding portion of the second fin structure is greater than a total height of the stack of nanostructures.

6. The semiconductor device structure as claimed in claim 1, further comprising a metal gate stack over the first fin structure, wherein the metal gate stack wraps around each of the nanostructures.

7. The semiconductor device structure as claimed in claim 6, wherein the metal gate stack comprises a gate dielectric layer, and a portion of the gate dielectric layer separates a bottom of the nanostructures from the first fin structure.

8. The semiconductor device structure as claimed in claim 7, wherein the metal gate stack comprises a work function layer, the gate dielectric layer is between the work function layer and the nanostructures, and a portion of the work function layer is between the bottom of the nanostructures and a top of the first fin structure.

9. The semiconductor device structure as claimed in claim 1, further comprising a metal gate stack over the second fin structure, wherein the metal gate stack comprises a gate dielectric layer, and a portion of the gate dielectric layer is between the embedded portion and the protruding portion.

10. The semiconductor device structure as claimed in claim 9, wherein the metal gate stack extends over the first fin structure, and a second portion of the gate dielectric layer is between the stack of the nanostructures and the first fin structure.

11. A semiconductor device structure, comprising:

a semiconductor substrate;

a stack of nanostructures, wherein the nanostructures are separated from each other; and

a fin structure over the semiconductor substrate, wherein a top of the fin structure is at a higher height level than a top of the nanostructures.

12. The semiconductor device structure as claimed in claim 11, further comprising a metal gate stack wrapping around each of the nanostructures and extending across the fin structure.

13. The semiconductor device structure as claimed in claim 12, wherein the metal gate stack comprises a gate dielectric layer, a first portion of the gate dielectric layer is between a bottom of the nanostructures and the semiconductor substrate, and a second portion of the gate dielectric layer is between a bottom of the fin structure and the semiconductor substrate.

14. The semiconductor device structure as claimed in claim 13, wherein the metal gate stack comprises a work function layer, a first portion of the work function layer is between the bottom of the nanostructures and the semiconductor substrate, and a second portion of the work function layer is between the bottom of the fin structure and the semiconductor substrate.

15. The semiconductor device structure as claimed in claim 11, further comprising:

an isolation structure over the semiconductor substrate;

a first embedded fin surrounded by the isolation structure and directly below the stack of the nano structures, wherein a top of the first embedded fin and a bottom of the nanostructures are separated from each other, and a total height of the nanostructures is greater than a total height of the first embedded fin; and

a second embedded fin surrounded by the isolation structure and directly below the fin structure, wherein a top of the second embedded fin and a bottom of the fin structure are separated from each other, and a total height of the fin structure is greater than a total height of the second embedded fin.

16. A method for forming a semiconductor device structure, comprising:

forming a sacrificial layer over a semiconductor substrate;

forming a semiconductor stack over a first region of the sacrificial layer, wherein the semiconductor stack has a plurality of first semiconductor layers and a plurality of second semiconductor layers laid out alternately;

forming a third semiconductor layer over a second region of the sacrificial layer;

patterning the semiconductor stack, the third semiconductor layer, and the sacrificial layer to form a first fin structure and a second fin structure, wherein the first fin structure comprises a portion of the semiconductor stack, and the second fin structure comprises a portion of the third semiconductor layer;

removing the sacrificial layer and the second semiconductor layers so that a plurality of nanostructures constructed by the first semiconductor layers are formed; and

forming a dielectric layer to wrap around each of the nanostructures and to wrap around the second fin structure.

17. The method for forming a semiconductor device structure as claimed in claim 16, wherein the dielectric layer is a gate dielectric layer of a metal gate stack.

18. The method for forming a semiconductor device structure as claimed in claim 16, wherein the sacrificial layer and the second semiconductor layers are removed simultaneously.

19. The method for forming a semiconductor device structure as claimed in claim 16, wherein a topmost layer of the semiconductor stack is one of the second semiconductor layers.

20. The method for forming a semiconductor device structure as claimed in claim 16, further comprising oxidizing the sacrificial layer and the second semiconductor layers before removing the sacrificial layer and the second semiconductor layers.