Test board for testing a semiconductor device utilizing first and second delay elements in a signal-transmission-path

• US 6,356,096 B2
• Filed: 09/03/1998
• Issued: 03/12/2002
• Est. Priority Date: 05/07/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ueda, Masahiro, Deguchi, Yoshinori, Takagi, Ryoichi
• Primary Examiner(s): Karlsen, Ernest
• Assistant Examiner(s): Kobert, Russell M.
• Application Number:
  US09/146,173
• Publication Number:
  US 20020011865A1
• Time in Patent Office: 1,286 Days
• Field of Search: 324/765, 324/617, 714/700, 714/745
• US Class Current: 324/756.07
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

A test board for testing a semiconductor device. The semiconductor device includes at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from the first input terminal to output an internal signal. The operation of the semiconductor device is controlled by a signal obtained from the second input terminal. The test board includes a first delay element for delaying a signal to be transmitted therethrough for a first signal propagation delay time and a second delay element for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from the first signal propagation delay time. A signal-transmission-path receives a first test signal and forms, a first signal transmission path along which the first test signal is transmitted through the first delay element to the first input terminal of the semiconductor device, and a second transmission path along which the first test signal is transmitted through the second delay element to the second input terminal of the semiconductor device.

Claims

1. A test system, comprising:

a semiconductor device to be tested, said semiconductor device including at least first and second input terminals and an input/output buffer cell for buffering a signal obtained from said first input terminal to output an internal signal, the operation of said semiconductor device controlled by a signal obtained from said second input terminal;

first delay means for delaying a signal to be transmitted therethrough for a first signal propagation delay time;

second delay means for delaying a signal to be transmitted therethrough for a second signal propagation delay time different from said first signal propagation delay time; and

signal-transmission-path forming means for receiving a first test signal and forming a first signal transmission path along which said first test signal is transmitted through said first delay means to said first input terminal of said semiconductor device, and a second transmission path along which said first test signal is transmitted through said second delay means to said second input terminal of said semiconductor device.

2. The test system according to claim 1, wherein said second signal propagation delay time is set longer than said first signal propagation delay time;

and further comprising;

third delay means for delaying a signal to be transmitted therethrough for a third signal propagation delay time; and

fourth delay means for delaying a signal to be transmitted therethrough for a fourth signal propagation delay time shorter than said third signal propagation delay time,

said signal-transmission path forming means forming said first and second signal transmission paths in a first test mode; and

in a second test mode, said signal-transmission-path forming means further receiving a second test signal and forming a third signal transmission path along which said second test signal is transmitted through said third delay means to said first input terminal of said semiconductor device, and a fourth signal transmission path along which said second test signal is transmitted through said fourth delay means to said second input terminal of said semiconductor device.

3. The test system according to claim 1, wherein said semiconductor device further includes an output terminal capable of outputting a signal obtained from said first input terminal at a setting of a predetermined condition, without logically processing said signal, and further comprisining:

third delay means for delaying a signal to be transmitted therethrough for a third signal propagation delay time;

fourth delay means for delaying a signal to be transmitted therethrough for a fourth signal pr opagation delay time equal to said third signal propagation delay time; and

tolerable-output-time delay means for delaying a signal to be transmitted therethrough for a predetermnined tolerable output time,

said signal-transmission-path forming means further receiving a second test signal,

in a first mode for testing an output time, said signal-transmission-path forming means forming a first signal transmission path for testing an output time, capable of outputting a signal obtained by transmitting said second test signal through said fourth delay means and said tolerable-output-time delay means, to the outside as a first comparison signal,

in a second mode for testing an output time, said signal-transmission-path forming means forming second and third signal propagation paths for testing an output time, along which said first and said second test signals are transmitted through said third and said fourth delay means to said first and said second input terminals, respectively, and a fourth signal transmission path for testing an output time, capable of outputting a signal obtained from said output terminal to the outside as a second comparison signal.

4. The test board according to claim 1, wherein

said signal-propagation-path forming means, in said first test mode, terminates said first and said second input terminals via first and second terminating resistors, respectively.

5. The test board according to claim 1, wherein

said second input terminal includes first and second differential input terminals;

the operation of said semiconductor device is controlled by a signal obtained from said first and said second differential input terminals; and

said signal-transmission-path forming means, in said first test mode, applies said first test signal through said second delay means to said first differential input terminal of said second input terminal of said semiconductor device, and applies a fixed voltage to said second differential input terminal.

6. The test board according to claim 5, wherein

said signal-transmission-path forming means, in said first test mode, terminates said first input terminal via a first terminating resistor, and connects said first and said second differential input terminals with a resistance element.

7. The test system according to claim 1, wherein

said first and said second signal transmission paths are formed in such a manner that a transmission path of said first test signal branches into two with a magnetic relay, an MOS transistor, or a power splitter.

8. The test system according to claim 1, wherein

said first and said second delay means are formed of an axial cable determining a delay time according to its length, or an active delay element capable of setting a delay time through a predetermined setting operation.