Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions

• US 6,396,101 B2
• Filed: 04/16/2001
• Issued: 05/28/2002
• Est. Priority Date: 09/11/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Vajana, Bruno, Galbiati, Nadia, Libera, Giovanna Dalla, Patelmo, Matteo
• Primary Examiner(s): Wille, Douglas
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US09/836,590
• Publication Number:
  US 20010021556A1
• Time in Patent Office: 407 Days
• Field of Search: 438/201,211,257,258,264,299 257/314,315,316,319,320,321,322
• US Class Current: 257/316
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND

Abstract

A method for manufacturing electronic devices, such as memory cells and LV transistors, with salicided junctions, that includes: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining floating gate regions on first areas, LV gate regions on second areas of a substrate, and undefined regions on the first and third areas of the substrate; forming first cell source regions laterally to the floating gate regions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining HV gate regions on the third areas, and selection gate regions on the first areas; forming source regions laterally to the selection gate regions, and source and drain regions laterally to the HV gate regions.

Claims

1. An electronic device comprising an EEPROM cell, including a selection transistor and a memory transistor, formed in and on a substrate with a first conductivity type;

said memory transistor having a cell structure forming a control gate region and a floating gate region, a first conductive region formed in said substrate of semiconductor material with a second conductivity type on a first side of said cell structure, said first conductive region being overlaid by a silicide region;

said selection transistor comprising a selection gate region, a second and a third conductive region with said second conductivity type formed in said substrate, said third conductive region being arranged on a second side of said cell structure of said memory transistor;

said first and third conductive regions are offset with respect to said floating gate region of said memory transistor wherein said second and third conductive regions are not overlaid by the silicide region.

2. The device of claim 1, comprising a low voltage transistor having salicided source and drain regions.

3. The device of claim 1 wherein said silicide regions are arranged on said gate structure and on said control gate region.

4. The device of claim 3 wherein said floating gate region has a first length;

said control gate region has a second length shorter than said first length;

said spacer elements extend on both sides of said cell structure of said memory transistor; and

said first conductive region is aligned with one of said spacer elements.

5. An integrated electronic device, comprising:

a silicon substrate having active regions of LV conductivity and the HV conductivity formed therein, one or more LV transistors formed in the LV conductivity regions, one or more HV transistors formed in the HV conductivity regions, and an EEPROM memory cell formed in the HV conductivity regions;

each LV transistor having LV drain and source regions formed in the silicon substrate and the LV gate region formed on the silicon substrate, with silicide regions arranged on an indirect contact with the LV drain, source and gate regions; and

each HV transistor having HV source and drain regions formed in the silicon substrate that are not overlaid by silicide regions, and an HV gate region formed on the silicon substrate and arranged directly below a silicide region; and

an EEPROM cell, including a selection transistor and a memory transistor formed in the HV conductivity regions, the memory transistor having a cell structure forming a control gate region and a floating gate region, a first conductive region formed in the silicon substrate with a second conductivity type on a first side of the cell structure, the first conductivity region being overlaid by a silicide region;

the selection transistor comprising a selection gate region, a second and third conductive region with second conductivity type formed in the silicon substrate, and a third conductive region being arranged on a second side of the cell structure of the memory transistor, the first and third conductive regions formed offset with respect to the floating gate region of the memory transistor.

6. The device of claim 5 wherein the silicide regions are formed on the LV gate region, HV gate region, selection gate and on the control gate region.

7. The device of claim 6 wherein the floating gate region has a first length, the control gate region has a second length shorter than the first length, and the spacer elements extend on both sides of the cell structure of the memory transistor, and the first conductive region is aligned with one of the spacer elements.