Bias network for high efficiency RF linear power amplifier

• US 6,404,287 B2
• Filed: 07/02/2001
• Issued: 06/11/2002
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Dening, David C., Jorgenson, Jon D.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/897,567
• Publication Number:
  US 20010040483A1
• Time in Patent Office: 344 Days
• Field of Search: 330/296, 330/289, 330/288, 330/285
• US Class Current: 330/296
• CPC Class Codes: H03F 1/302 in bipolar transistor amplifiers H03F1/303, H03F1/305, H03F1/307 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal

Abstract

A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

Claims

1. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a collector, emitter and base;

a capacitor having one end coupled to the base of the bipolar junction transistor and having an opposite end configured to receive a radio frequency signal;

a second bipolar junction transistor having a base, a collector and an emitter, wherein the collector is coupled to a dc supply voltage;

a first resistor having one end coupled to the base of the second bipolar junction transistor and having an opposite end coupled to a bias voltage source;

a second resistor having a first end coupled to the emitter and having a second end coupled to the base of the radio frequency bipolar junction transistor,

the second resistor having a resistance value rendering the linear amplifier bias network capable of minimizing gain expansion associated with the radio-frequency bipolar junction transistor; and

a third resistor having one end coupled to the bias voltage source and having an opposite end coupled to the second end of the second resistor, wherein the second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic.

2. A linear amplifier bias network comprising according to claim 1 further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node;

a fourth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; and

a fifth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor;

wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

3. The linear amplifier bias network according to claim 2 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.

4. The linear amplifier bias network according to claim 2 wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

5. The linear amplifier bias network according to claim 4 wherein the diode network comprises a plurality of diodes and a series resistor.

6. The linear amplifier bias network according to claim 2 wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

7. The linear amplifier bias network according to claim 6 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

8. The linear amplifier bias network according to claim 7 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

9. The linear amplifier bias network according to claim 8 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

10. The linear amplifier bias network according to claim 8 wherein any single resistor selected from the ground consisting of the first, second, third, fourth .and fifth resistors is configured to have zero resistance.

11. The linear amplifier bias network according to claim 1 further comprising:

a ground node; and

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the base and collector of the third bipolar junction transistor are coupled to the second end of the second resistor.

12. The linear amplifier bias network according to claim 11 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.

13. The linear amplifier bias network according to claim 11 wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

14. The linear amplifier bias network according to claim 13 wherein the diode network comprises a plurality of diodes and a series resistor.

15. The linear amplifier bias network according to claim 10 wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

16. The linear amplifier bias network according to claim 15 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

17. The linear amplifier bias network according to claim 16 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

18. The linear amplifier bias network according to claim 17 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

19. The linear amplifier bias network according to claim 17 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

20. The linear amplifier bias network according to claim 19 wherein any single resistor selected from the group consisting of the first, second and third resistors is configured to have zero resistance.

21. The linear amplifier bias network according to claim 1 further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the node and wherein the collector of the third bipolar junction transistor is coupled to the second end of the second resistor; and

a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second, third and fourth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expansion associated with the radio frequency bipolar junction transistor.

22. The linear amplifier bias network according to claim 21 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage to generate a desired supply reference voltage.

23. The linear amplifier bias network according to claim 21 wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

24. The linear amplifier bias network according to claim 23 wherein the diode network comprises a plurality of diodes and a series resistor.

25. The linear amplifier bias network according to claim 21 wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

26. The linear amplifier bias network according to claim 25 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

27. The linear amplifier bias network according to claim 26 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

28. The linear amplifier bias network according to claim 27 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

29. The linear amplifier bias network according to claim 27 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

30. The linear amplifier bias network according to claim 29 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

31. The linear amplifier bias network according to claim 1 further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node and wherein the base of the third bipolar junction transistor is coupled to the second end of the second resistor; and

a fourth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second, third and fourth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current and minimize gain expression associated with the radio frequency bipolar junction transistor.

32. The linear amplifier bias network according to claim 31 wherein the bias voltage storage comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired supply reference voltage.

33. The linear amplifier bias network according to claim 31 wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

34. The linear amplifier bias network according to claim 33 wherein the diode network comprises a plurality of diodes and a series resistor.

35. The linear amplifier bias network according to claim 31 wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

36. The linear amplifier bias network according to claim 35 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

37. The linear amplifier bias network according to claim 36 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

38. The linear amplifier bias network according to claim 37 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

39. The linear amplifier bias network according to claim 37 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

40. The linear amplifier bias network according to claim 39 wherein any single resistor selected from the group consisting of the first, second, third and fourth resistors is configured to have zero resistance.

41. A linear amplifier bias network comprising:

a radio frequency bipolar junction transistor having a base, collector and emitter;

a capacitor having one end coupled to the base of the radio frequency bipolar junction transistor and having an opposite end configured to receive a radio frequency input signal;

a second bipolar junction transistor having a base, collector and emitter, wherein the collector of the second bipolar junction transistor is coupled to a dc supply voltage;

a first resistor having one end coupled to the base of the second bipolar junction transistor and an opposite end coupled to a bias voltage source;

a second resistor having one end coupled to the emitter of the second bipolar junction transistor and having a second end configured to supply a bias current; and

a third resistor having one end coupled to the bias voltage source and an opposite end coupled to the second end of the second resistor, wherein a combination of resistance values for the first, second and third resistors render the linear amplifier bias network capable of minimizing gain expansion associated with the radio frequency bipolar junction transistor and further wherein a combination of resistance values for the first, second and third resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

42. The linear amplifier bias network according to claim 41 further comprising:

a ground node;

a third bipolar junction transistor having a base, collector and emitter, wherein the emitter of the third bipolar junction transistor is coupled to the ground node;

a fourth resistor having one end coupled to the base of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor; and

a fifth resistor having one end coupled to the collector of the third bipolar junction transistor and having an opposite end coupled to the second end of the second resistor;

wherein a combination of resistance values for the first, second, third, fourth and fifth resistors are capable of adjusting a bias impedance associated with the bias network such that the bias network can achieve a desired temperature compensation characteristic and further such that the bias network can achieve a desired level of quiescent current associated with the radio frequency bipolar junction transistor.

43. The linear amplifier bias network according to claim 42 wherein the bias voltage source comprises a resistor/diode network coupled to a supply voltage and configured to generate a desired reference supply voltage.

44. The linear amplifier bias network according to claim 42 wherein the bias voltage source comprises:

a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the diode network such that a predetermined voltage drop is achieved across the diode network relative to the ground node to produce a desired bias voltage for the linear amplifier bias network.

45. The linear amplifier bias network according to claim 44 wherein the diode network comprises a plurality of diodes and a series resistor.

46. The linear amplifier bias network according to claim 42 wherein the bias voltage source comprises:

a transistor network configured as a diode network; and

a resistor having a first end coupled to a supply voltage and having an opposite end coupled to the transistor network such that a predetermined voltage drop is achieved across the transistor network relative to the ground node to produce a desired supply reference voltage for the linear amplifier bias network.

47. The linear amplifier bias network according to claim 46 wherein the transistor network comprises a plurality of bipolar junction transistors and a series resistor.

48. The linear amplifier bias network according to claim 47 further comprising an inductor having a first end coupled to the ground node and further having an opposite end coupled to the emitter of the third bipolar junction transistor such that the emitter of the third bipolar junction transistor is coupled to the ground node solely through the inductor.

49. The linear amplifier bias network according to claim 48 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.

50. The linear amplifier bias network according to claim 48 wherein the emitter of the third bipolar junction transistor is further coupled to the transistor network such that a portion of the transistor network is coupled to the ground node solely through the inductor.

51. The linear amplifier bias network according to claim 50 wherein any single resistor selected from the group consisting of the first, second, third, fourth and fifth resistors is configured to have zero resistance.