Refresh control circuit for low-power SRAM applications
First Claim
1. A semiconductor static random access memory (SRAM) system including one or more memory arrays, said system comprising;
- a power management device associated with each memory array, each power management device comprising a first switching device for connecting an external Power source to a memory array during normal SRAM device operation and responsive to a low power mode signal for disconnecting said external power source from said memory array during a low power mode of operation;
said power management device further comprising a second switching device for connecting said external power source to a local power source associated with each respective memory array, and, a refresh control device for independently controlling each said second switch device for selectively connecting and disconnecting said external power source to said local power source associated with a respective memory array for refreshing said associated local power source during said low power mode of operation, whereby power consumption in said SRAM device is reduced during said low power mode.
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Accused Products
Abstract
A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.
52 Citations
26 Claims
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1. A semiconductor static random access memory (SRAM) system including one or more memory arrays, said system comprising;
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a power management device associated with each memory array, each power management device comprising a first switching device for connecting an external Power source to a memory array during normal SRAM device operation and responsive to a low power mode signal for disconnecting said external power source from said memory array during a low power mode of operation;
said power management device further comprising a second switching device for connecting said external power source to a local power source associated with each respective memory array, and,a refresh control device for independently controlling each said second switch device for selectively connecting and disconnecting said external power source to said local power source associated with a respective memory array for refreshing said associated local power source during said low power mode of operation, whereby power consumption in said SRAM device is reduced during said low power mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
a first comparing device for comparing said sensed local power supply level against said predetermined high-level voltage;
a second comparing device for comparing said sensed local power supply level against said predetermined low-level voltage, each of said comparing devices connected with said means responsive to said first and second comparing devices for one of;
respectively deactivate and activate said second switch device for respectively disconnecting said external power supply from said local supply or connecting said external power supply to said local supply.
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20. The SRAM system as claimed in claim 19, wherein said means responsive to said first and second comparing devices includes a flip-flop device.
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21. The SRAM system as claimed in claim 1, further comprising ground wiring provided to shield noise among said one or more memory arrays.
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22. A power management circuit for an SRAM system including one or more memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to each local power supply during active mode of operation, said power management circuit comprising:
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a switch mechanism for disconnecting the external power supply to each said at least one local power supply during a low power mode of operation; and
,a refresh timing circuit implementing memory cell refresh operation by selectively connecting the external power supply to a respective local power supply during said low power mode, wherein, during said low power mode, said refresh circuit intentionally enables said local power supply to float and drift to a lower predetermined voltage level prior to said memory array refresh operation.
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23. A power management circuit for an SRAM system including one or more memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to each local power supply during active mode of operation, said power management circuit comprising:
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a first switch mechanism for disconnecting the external power supply to each said at least one local power supply during a low power mode of operation; and
,a refresh timing circuit implementing a voltage clamp device for clamping said each respective local power supply at a predetermined voltage during said low power mode, said predetermined voltage being lower than said external supply voltage. - View Dependent Claims (24, 25, 26)
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Specification