Semiconductor device and method of manufacturing the same

• US 6,476,454 B2
• Filed: 03/26/2001
• Issued: 11/05/2002
• Est. Priority Date: 03/27/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suguro, Kyoichi
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/816,171
• Publication Number:
  US 20010025999A1
• Time in Patent Office: 589 Days
• Field of Search: 257/388, 257/411, 257/412, 257/410, 257/6, 257/382, 257/377, 257/384, 257/368, 257/369
• US Class Current: 257/410
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26593 at a temperature lower than room temperature
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating film and a gate electrode formed on the semiconductor substrate, source-drain regions formed in the semiconductor substrate, and a metal oxide layer formed selectively on the gate electrode. The gate electrode is formed of a first metal, and the metal oxide layer contains a second metal having a reduction amount of a Gibbs standard free energy in forming an oxide that is larger than that of the first metal.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

an insulating film formed on said semiconductor substrate and a gate electrode formed on said insulating film;

source-drain regions formed in said semiconductor substrate;

a metal oxide layer formed selectively on said gate electrode; and

an interlayer insulating film formed of a silicon oxide film;

wherein said gate electrode is formed of a first metal, and said metal oxide layer contains a second metal having a reduction amount in a Gibbs standard free energy in forming an oxide larger than that of said first metal, and

wherein said second metal has a reduction amount in a Gibbs standard free energy in forming an oxide that is larger than that of the material forming said interlayer insulating film.

2. The semiconductor device according to claim 1, wherein said first metal consists of at least one element selected from the group consisting of W, Mo, Ru, Ag and Cu.

3. The semiconductor device according to claim 1, wherein said second metal consists of at least one element selected from the group consisting of Al, Ti, Zr, Hf, Nb, Ta, Ba, Sr, Y and La series elements.

4. The semiconductor device according to claim 1, wherein said metal oxide layer has a thickness of 1 to 50 nm.

5. The semiconductor device according to claim 1, further comprising a layer of a third metal or a compound of said third metal formed on the bottom surface of said gate electrode, said third metal not being alloyed or not forming a compound with said first metal and the crystal grain diameter of said third metal being smaller than that of said first metal.

6. The semiconductor device according to claim 1, further comprising a layer of a third metal or a compound of said third metal formed on the bottom surface and side surface of said gate electrode, said third metal not being alloyed or not forming a compound with said first metal and the crystal grain diameter of said third metal being smaller than that of said first metal.

7. The semiconductor device according to claim 2, wherein said second metal consists of at least one element selected from the group consisting of Al, Ti, Zr, Hf, Nb, Ta, Ba, Sr, Y and La series elements.

8. The semiconductor device according to claim 2, wherein said metal oxide layer has a thickness of 1 to 50 nm.

9. The semiconductor device according to claim 3, wherein said metal oxide layer has a thickness of 1 to 50 nm.

10. A semiconductor device, comprising:

a semiconductor substrate;

an insulating film formed on said semiconductor substrate and a gate electrode formed on said insulating film;

source-drain regions formed in said semiconductor substrate;

a metal oxide layer formed selectively on said gate electrode; and

an interlayer insulating film including a silicon oxide film;

wherein said gate electrode is formed of a first metal, and said metal oxide layer contains a second metal having a reduction amount in a Gibbs standard free energy in forming an oxide larger than that of said first metal, and

wherein said second metal has a reduction amount in a Gibbs standard free energy in forming an oxide that is larger than that of the material forming said interlayer insulating film.

11. The semiconductor device according to claim 10, wherein said first metal consists of at least one element selected from the group consisting of W, Mo, Ru, Ag and Cu.

12. The semiconductor device according to claim 10, wherein said second metal consists of at least one element selected from the group consisting of Al, Ti, Zr, Hf, Nb, Ta, Ba, Sr, Y and La series elements.

13. The semiconductor device according to claim 10, wherein said metal oxide layer has a thickness of 1 to 50 nm.

14. The semiconductor device according to claim 10, further comprising a layer of a third metal or a compound of said third metal formed on the bottom surface of said gate electrode, said third metal not being alloyed or not forming a compound with said first metal and the crystal grain diameter of said third metal being smaller than that of said first metal.

15. The semiconductor device according to claim 10, further comprising a layer of a third metal or a compound of said third metal formed on the bottom surface and side surface of said gate electrode, said third metal not being alloyed or not forming a compound with said first metal and the crystal grain diameter of said third metal being smaller than that of said first metal.

16. The semiconductor device according to claim 11, wherein said second metal consists of at least one element selected from the group consisting of Al, Ti, Zr, Hf, Nb, Ta, Ba, Sr, Y and La series elements.

17. The semiconductor device according to claim 11, wherein said metal oxide layer has a thickness of 1 to 50 nm.

18. The semiconductor device according to claim 12, wherein said metal oxide layer has a thickness of 1 to 50 nm.