Multiple stream variable length encoder and decoder

• US 6,498,571 B2
• Filed: 12/08/2000
• Issued: 12/24/2002
• Est. Priority Date: 12/09/1999
• Status: Expired due to Fees

• Current Assignee: Luxxon Corp.
• Original Assignee: Luxxon Corp.
• Inventors: Molloy, Stephen A.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US09/734,236
• Publication Number:
  US 20020006172A1
• Time in Patent Office: 746 Days
• Field of Search: 341/65, 341/67, 395/410, 395/412, 395/416
• US Class Current: 341/65
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/6125 involving transmission via Internet transmission by internet of broadcast information H04H60/82
• CPC Class Codes: H04N 21/6175 involving transmission via Internet broadcast-related systems characterised by the transmission system being the Internet H04H60/82
• CPC Class Codes: H04N 7/17318 Direct or substantially direct transmission and handling of requests
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

An apparatus may include a first plurality of registers, each register in the first plurality of registers configured to store data wordss, a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal, a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers, a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plurality of registers, a shift register coupled to the first selector and to the second selector circuit, the shift register configured to receive the data words from the selected register in the first plurality of registers, configured to receive the pointer, and configured to output a portion of the data words, the portion of the data words determined by the pointer, and a decoder coupled to the shift register, the decoder configured to receive the portion of the data words, and configured to output decoded data in response to the portion of the data words.

Claims

1. An apparatus comprises:

a first plurality of registers, each register in the first plurality of registers configured to store data packets;

a first selector coupled to the first plurality of registers, the first selector configured to receive a data packet stored in each register in the first plurality of registers, and configured to output the data packet from a selected register from the first plurality of registers in response to a selection signal;

a second plurality of registers, each register in the second plurality of registers configured to store a pointer associated with each register in the first plurality of registers;

a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising a pointer associated with the selected register from the first plurality of registers;

a shifter coupled to the first selector and to the second selector circuit, the shifter configured to receive the data packet from the selected register in the first plurality of registers, configured to receive the pointer, and configured to output a portion of the data packet, the portion of the data packet determined by the pointer; and

a decoder coupled to the shifter, the decoder configured to receive the portion of the data packet, and configured to output decoded data in response to the portion of the data packet.

2. The apparatus of claim 1

wherein a data packet stored in the selected register comprises data from a first data source; and

wherein a data packet stored in another register comprises data from a second data source.

3. The apparatus of claim 1

wherein a data packet stored in a first register comprises data from a data source stored in a forward direction from a data source;

and

wherein a data packet stored in a second register comprises the data from the data source stored in a reverse direction.

4. The apparatus of claim 2 further comprising

a channel selector coupled to the first selector and to the second selector, the channel selector configured to assert the selection signal when the data from the first data source is to be decoded.

5. The apparatus of claim 1

wherein the portion of the data packet is encoded in a Huffman encoding scheme;

and

wherein the decoder is configured to decode Huffman encoded data.

6. The apparatus of claim 1

a third plurality of registers, each register in the third plurality of registers configured to store additional data packets;

a third selector coupled to the third plurality of registers, the third selector configured to receive an additional data packet stored in each register in the third plurality of registers, and configured to output the additional data packet from a selected register from the third plurality of registers in response to a selection signal;

wherein the shifter is also coupled to the third selector, and the shifter is also configured to receive the additional data packet, and is also configured to output a portion of the additional data packet, the portion of the additional data packet determined by the pointer; and

wherein the decoder is also configured to receive the portion of the additional data packet, and is configured to output decoded data in response to the portion of the data packet and to the portion of the additional data packet.

7. The apparatus of claim 1 further comprising a third selector coupled to the shifter and coupled to the decoder, the third selector configured to receive the portion of the data packet, the portion of the additional data packet, and the output decoded data, and the third selector configured to output the portion of the data packet and the portion of the additional data packet or the output decoded data in response to a mode selection signal.

8. A method for decoding streams of encoded data comprises:

receiving a first stream of encoded data, the first stream from a first source;

receiving a second stream of encoded data, the second stream from a second source;

storing a first set of data in a first register, the first set of data from the first stream of encoded data;

storing a second set of data in a second register, the second set of data from the second stream of encoded data;

storing a first pointer in a third register, the first pointer associated with the first set of data;

storing a second pointer in a fourth register, the second pointer associated with the second set of data;

applying a first signal to a selector;

when the first signal is applied to the selector, coupling the first register and the third register to a shifter, and outputting data with the shifter, the data comprising a portion of the first set of data in response to the first pointer;

when the first signal is not applied to the selector, coupling the second register and the fourth register to the shifter, and outputting data with the shifter, the data comprising a portion of the second set of data in response to the second pointer; and

decoding the data from the shifter and outputting decoded data.

9. The method of claim 8

wherein decoding the data from the shifter also comprises outputting a code length; and

wherein the method further comprises when the first signal is applied to the selector, updating the first pointer in the third register in response to the code length.

10. The method of claim 8 wherein decoding the data comprises performing a Huffman decoding on the data from the shifter.

11. The method of claim 8

wherein when the first signal is applied to the selector, outputting data with the shifter comprises outputting a string of bits from the first set of data, an end bit from the string of bits determined by the first pointer;

wherein a number of bits in the string of bits is predetermined.

12. The method of claim 8

updating the first set of data stored in the first register in response to data from the first stream and to the code length.

13. The method of claim 8

wherein the first stream of encoded data and the second stream of encoded data are bit reversed relative to each other.

14. An encoding apparatus configured to receive data input from data sources and offsets associated with the data sources comprises

a first plurality of registers, each register in the first plurality of registers configured to store data wordss;

a first selector coupled to the first plurality of registers, the first selector configured to receive a data words stored in each register in the first plurality of registers, and configured to output the data words from a selected register from the first plurality of registers in response to a selection signal;

a second plurality of registers, each register in the second plurality of registers configured to store a pointer;

a second selector coupled to the second plurality of registers, the selector circuit configured to receive data from each register in the second plurality of registers, and configured to output data from a selected register from the second plurality of registers in response to the selection signal, the data comprising pointers associated with the data sources;

an accumulator coupled to the second selector, the accumulator configured to combine the pointers associated with the data sources and the offsets;

a shift register coupled to the accumulator, the shift register configured to receive the data input, configured to receive output from the accumulator, and configured to output the data input at a shifted position in response to the output from the accumulator; and

a logic circuit coupled to the shift register and to the first selector, the logic circuit configured to perform a logic function on the data words from the selected register and output from the shift register;

wherein the first plurality of registers is also coupled to the logic circuit and the first plurality of registers is configured to store output from the logic circuit.

15. The encoding apparatus of claim 14 wherein the accumulator is also configured to assert an overflow condition.

16. The encoding apparatus of claim 14 further comprising:

a third plurality of registers coupled to the logic circuit, each register in the third plurality of registers configured to store the output from the logic circuit; and

a third selector coupled to the third plurality of registers, the third selector configured to receive a data words stored in each register in the third plurality of registers, and configured to output the data words from a selected register from the third plurality of registers in response to the selection signal.

17. The encoding apparatus of claim 16 further comprising a controller coupled to the third plurality of registers and to the accumulator, the controller configured to cause the data words from the selected register from the third plurality of registers to be stored in the selected register from the first plurality of registers.

18. The encoding apparatus of claim 14 wherein the offsets are selected from the group:

a fixed length, a variable length.

19. The encoding apparatus of claim 18 wherein the data input from data sources and offsets associated with the data sources are output from a codebook circuit.

20. The encoding apparatus of claim 19 wherein the codebook circuit implements a Huffman encoding process.

21. The encoding apparatus of claim 14 wherein the first plurality of registers comprise a register file including the first selector.