Memory read circuitry

• US 6,512,712 B1
• Filed: 07/17/2001
• Issued: 01/28/2003
• Est. Priority Date: 07/17/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Tawari, Devendra N., Desai, Shaishav A.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Pham, Ly Duy
• Application Number:
  US09/908,667
• Publication Number:
  US 20030016579A1
• Time in Patent Office: 560 Days
• Field of Search: 365/194, 365/203, 365/189.08
• US Class Current: 365/203
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A circuit on a semiconductor for precharging a local bitline and a global bitline. The circuit includes: a precharge input; a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline; a delay element, the input of the delay element coupled to the precharge input; and a second switch, the gate of the second switch coupled to the output of the delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline.

Claims

1. A circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit comprising:

a) a precharge input;

b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;

c) a first delay element, the input of the first delay element coupled to the precharge input;

d) a second delay element, the input of the second delay element coupled to the output of the first delay element;

e) a second switch, the gate of the second switch coupled to the output of the first delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline; and

f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source.

2. The circuit for precharging a local bitline and a global bitline of claim 1, wherein the first switch is a metal oxide semiconductor transistor.

3. The circuit for precharging a local bitline and a global bitline of claim 1, wherein the first switch is a p-type metal oxide semiconductor transistor.

4. The circuit for precharging a local bitline and a global bitline of claim 1, wherein the delay element is an inverter.

5. The circuit for precharging a local bitline and a global bitline of claim 1, wherein the delay element includes two inverters.

6. The circuit for precharging a local bitline and a global bitline of claim 1, wherein the second switch is a metal oxide semiconductor transistor.

7. The circuit for precharging a local bitline and a global bitline of claim 1, wherein the second switch is a p-type metal oxide semiconductor transistor.

8. A computer system comprising:

a) a central processing unit, the central processing unit including a circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit including;

1) a precharge input;

2) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;

3) a first delay element, the input of the first delay element coupled to the precharge input;

4) a second delay element, the input of the second delay element coupled to the output of the first delay element;

5) a second switch, the gate of the second switch coupled to the output of the first delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline; and

6) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source.

9. A Dynamic Random Access Device (DRAM), the DRAM including a circuit on a semiconductor for precharging a local bitline and a global bitline, the circuit including:

a) a precharge input;

b) a first switch, the gate of the first switch coupled to the precharge input, the source of the first switch coupled to a voltage source, the drain of the first switch coupled to the local bitline;

c) a first delay element, the input of the first delay element coupled to the precharge input;

d) a second delay element, the input of the second delay element coupled to the output of the first delay element;

e) a second switch, the gate of the second switch coupled to the output of the first delay element, the source of the second switch coupled to the voltage source, the drain of the second switch coupled to the global bitline; and

f) a third switch, the gate of the third switch coupled to the output of the first delay element, the source of the third switch coupled to the voltage source.