6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE SUBSTRATE, A METHOD OF FORMING MEMORY CELLS IN A 6F2 DRAM ARRAY AND A METHOD OF ISOLATING A SINGLE ROW OF MEMORY CELLS IN A 6F2 DRAM ARRAY

• US 6,545,904 B2
• Filed: 03/16/2001
• Issued: 04/08/2003
• Est. Priority Date: 03/16/2001
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Tran, Luan C.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/810,933
• Publication Number:
  US 20020130348A1
• Time in Patent Office: 753 Days
• Field of Search: 365/149, 365/63, 365/51, 257/69, 257/71, 257/905, 257/906
• US Class Current: 365/149
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

The present invention includes a 6F² DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

Claims

1. A 6F² DRAM array including:

a first memory cell including a first access transistor and a first data storage capacitor, a first load electrode of the first access transistor being coupled to the first data storage capacitor via a first storage node formed on a substrate;

a second memory cell including a second access transistor and a second data storage capacitor, a first load electrode of the second access transistor being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access transistors each including a first gate dielectric with a first thickness; and

an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate including a second gate dielectric comprising an isolation gate dielectric with a second thickness that is greater than the first thickness used in at least the access transistors.

2. The 6F² DRAM array of claim 1, wherein the second gate dielectric is formed by a deposition process in a shallow trench.

3. The 6F² DRAM array of claim 1, wherein the second thickness is between thirty percent and seventy percent thicker than the first thickness.

4. The 6F² DRAM array of claim 1, wherein the first thickness is about fifty Angstroms, and the second thickness is in a range of from about seventy Angstroms to about one hundred Angstroms.

5. The 6F² DRAM array of claim 1, wherein the first and second gate dielectrics comprise silicon dioxide.

6. The 6F² DRAM array of claim 1, wherein each of the access transistors includes a second load electrode coupled to a respective bitline contact, and wherein each of the access transistors has a threshold voltage determined in part by a halo implant on a bitline contact side only of the access transistor.

7. A DRAM array formed on a semiconductive substrate and including:

a first memory cell including a first access device and a first data storage capacitor, a first load electrode of the first access device being coupled to the first data storage capacitor via a first storage node formed on the substrate;

a second memory cell including a second access device and a second data storage capacitor, a first load electrode of the second access device being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access devices having a first threshold voltage; and

an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate having a second threshold voltage that is greater than the first threshold voltage.

8. The DRAM array of claim 7, wherein:

the first and second access devices each include a second load electrode coupled to a respective bitline, a gate coupled to a respective wordline and a gate dielectric separating the gate from the substrate, each gate dielectric having a first thickness; and

the isolation gate comprises a portion of an isolation device that includes a first load electrode corresponding to the first storage node, a second load electrode corresponding to the second storage node, a gate coupled to a voltage configured to turn the isolation device OFF and an isolation gate dielectric separating the gate from the substrate, the isolation gate dielectric having a second thickness greater than the first thickness.

9. The DRAM array of claim 7, wherein second load electrodes of the first and second access devices are coupled to bitline contacts and have been angle implanted.

10. The DRAM array of claim 7, wherein each of the first and second memory cells has an area of 6F², wherein F is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus a width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array.

11. The DRAM array of claim 7, wherein the isolation gate comprises a portion of an isolation transistor that includes a first load electrode corresponding to the first storage node, a second load electrode corresponding to the second storage node, a gate coupled to a voltage configured to turn the isolation gate OFF and a gate dielectric separating the gate from the substrate, the gate dielectric being formed in a shallow trench.

12. The DRAM array of claim 7, wherein:

the first and second access devices each include a second load electrode coupled to a respective bitline, a gate coupled to a respective wordline and a gate dielectric separating the gate from the substrate, each gate dielectric having a first thickness of about fifty Angstroms; and

the isolation gate comprises a portion of an isolation device that includes a first load electrode corresponding to the first storage node, a second load electrode corresponding to the second storage node, a gate coupled to a voltage configured to turn the isolation device OFF and an isolation gate dielectric separating the gate from the substrate, the isolation gate dielectric having a second thickness in a range of from about seventy Angstroms to about one hundred Angstroms.

13. A method of isolating a single row of memory cells in a 6F² DRAM array comprising:

providing pairs of rows of memory cells, each row including a plurality of access devices each having a gate dielectric with a first thickness; and

providing an isolation gate separating rows comprising each pair of rows, each isolation gate having a gate dielectric with a second thickness, the second thickness being greater than the first thickness, the isolation gates being configured to isolate one of the pair of rows from another of the pair of rows in response to application of a suitable voltage.

14. The method of claim 13, wherein providing access devices in each of the rows comprises providing access devices having a threshold voltage determined in part by a halo implant on a bit contact side only of the access device.

15. The method of claim 13, wherein providing access devices in each of the rows comprises providing access devices having a gate dielectric comprising an oxide having a thickness of about fifty Angstroms.

16. The method of claim 13, wherein:

providing access devices in each of the rows comprises providing access devices having a first threshold voltage having a first magnitude; and

providing pairs of rows of memory cells comprises providing rows of memory cells, each pair of rows being separated by an isolation gate having a second threshold voltage having a magnitude greater than the first threshold voltage.

17. The method of claim 13, wherein providing an isolation gate comprises:

forming a shallow trench;

forming an initial dielectric filling the trench;

planarizing the initial dielectric to provide the isolation gate dielectric; and

forming a gate atop the isolation gate dielectric.

18. The method of claim 17, further comprising implanting dopant into the shallow trench prior to forming an initial dielectric.

19. The method of claim 13, wherein providing an isolation gate comprises:

forming an initial oxide via a thermal oxidation process;

stripping the initial oxide from areas that will become access devices; and

performing another thermal oxidation to provide isolation gate dielectric material having one thickness in isolation gate areas and to provide another gate dielectric material having another thickness that is less than the one thickness in access device gate areas.

20. The method of claim 13, wherein providing an isolation gate comprises providing an isolation gate configured to be coupled to a negative voltage, thus reducing subthreshold leakage by further reducing gate induced drain leakage.

21. A memory array including:

a first memory cell including a first access transistor and a first data storage element, a first load electrode of the first access transistor being coupled to the first data storage element via a first storage node formed on a substrate;

a second memory cell including a second access transistor and a second data storage element, a first load electrode of the second access transistor being coupled to the second data storage element via a second storage node formed on the substrate, the first and second access transistors each including a first gate dielectric with a first thickness; and

an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.

22. The memory array of claim 21, wherein the isolation gate includes a second gate dielectric comprising an isolation gate dielectric with a second thickness that is greater than the first thickness used in at least the access transistors.

23. The memory array of claim 22, wherein the second gate dielectric is formed by a deposition process in a shallow trench.

24. The memory array of claim 22, wherein the second thickness is between thirty percent and seventy percent thicker than the first thickness.

25. The memory array of claim 22, wherein the first thickness is about fifty Angstroms, and the second thickness is in a range of from about seventy Angstroms to about one hundred Angstroms.

26. The memory array of claim 22, wherein the first and second gate dielectrics comprise silicon dioxide.

27. The memory array of claim 22, wherein each of the access transistors includes a second load electrode coupled to a respective bitline contact, and wherein each of the access transistors has a threshold voltage determined in part by a halo implant on a bitline contact side only of the access transistor.

28. The memory array of claim 21, wherein the data storage elements comprise capacitors.

29. A memory array including:

a first memory cell including a first access device and a first data storage element, a first load electrode of the first access device being coupled to the first data storage element via a first storage node formed on a substrate;

a second memory cell including a second access device and a second data storage element, a first load electrode of the second access device being coupled to the second data storage element via a second storage node formed on the substrate, the first and second access devices having a first threshold voltage; and

an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate having a second threshold voltage that is greater than the first threshold voltage.

30. The memory array of claim 29, wherein the first and second data storage elements comprise capacitors.

31. The memory array of claim 29, wherein:

the first and second access devices each include a second load electrode coupled to a respective bitline, a gate coupled to a respective wordline and a gate dielectric separating the gate from the substrate, each gate dielectric having a first thickness; and

the isolation gate comprises a portion of an isolation device that includes a first load electrode corresponding to the first storage node, a second load electrode corresponding to the second storage node, a gate coupled to a voltage configured to turn the isolation device OFF and an isolation gate dielectric separating the gate from the substrate, the isolation gate dielectric having a second thickness greater than the first thickness.

32. The memory array of claim 29, wherein second load electrodes of the first and second access devices are coupled to bitline contacts and have been angle implanted.

33. The memory array of claim 29, wherein each of the first and second memory cells comprise DRAM memory cells having an area of 6F², wherein F is defined as equal to one-half of minimum pitch, with minimum pitch being defined as equal to the smallest distance of a line width plus a width of a space immediately adjacent said line on one side of said line between said line and a next adjacent line in a repeated pattern within the array.

34. The memory array of claim 29, wherein the isolation gate comprises a portion of an isolation transistor that includes a first load electrode corresponding to the first storage node, a second load electrode corresponding to the second storage node, a gate coupled to a voltage configured to turn the isolation gate OFF and a gate dielectric separating the gate from the substrate, the gate dielectric being formed in a shallow trench.

35. The memory array of claim 29, wherein:

the first and second access devices each include a second load electrode coupled to a respective bitline, a gate coupled to a respective wordline and a gate dielectric separating the gate from the substrate, each gate dielectric having a first thickness of about fifty Angstroms; and

the isolation gate comprises a portion of an isolation device that includes a first load electrode corresponding to the first storage node, a second load electrode corresponding to the second storage node, a gate coupled to a voltage configured to turn the isolation device OFF and an isolation gate dielectric separating the gate from the substrate, the isolation gate dielectric having a second thickness in a range of from about seventy Angstroms to about one hundred Angstroms.

36. A method of isolating a row of memory cells in a memory array comprising:

providing pairs of rows of memory cells, each row including a plurality of access devices each having a gate dielectric with a first thickness; and

providing an isolation gate separating rows comprising each pair of rows, each isolation gate having a gate dielectric with a second thickness, the second thickness being greater than the first thickness, the isolation gates being configured to isolate one of the pair of rows from another of the pair of rows in response to application of a suitable voltage.

37. The method of claim 36, wherein providing access devices in each of the rows comprises providing access devices having a threshold voltage determined in part by a halo implant on a bit contact side only of the access device.

38. The method of claim 36, wherein providing access devices in each of the rows comprises providing access devices having a gate dielectric comprising an oxide having a thickness of about fifty Angstroms.

39. The method of claim 36, wherein:

providing access devices in each of the rows comprises providing access devices having a first threshold voltage having a first magnitude; and

providing pairs of rows of memory cells comprises providing rows of memory cells, each pair of rows being separated by an isolation gate having a second threshold voltage having a magnitude greater than the first threshold voltage.

40. The method of claim 36, wherein providing an isolation gate comprises:

forming a shallow trench;

forming an initial dielectric filling the trench;

planarizing the initial dielectric to provide the isolation gate dielectric; and

forming a gate atop the isolation gate dielectric.

41. The method of claim 40, further comprising implanting dopant into the shallow trench prior to forming an initial dielectric.

42. The method of claim 36, wherein providing an isolation gate comprises:

forming an initial oxide via a thermal oxidation process;

stripping the initial oxide from areas that will become access devices; and

performing another thermal oxidation to provide isolation gate dielectric material having one thickness in isolation gate areas and to provide another gate dielectric material having another thickness that is less than the one thickness in access device gate areas.

43. The method of claim 36, wherein providing an isolation gate comprises providing an isolation gate configured to be coupled to a negative voltage, thus reducing subthreshold leakage by further reducing gate induced drain leakage.