Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays
First Claim
1. A memory device comprising:
- a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array, and wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array.
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Accused Products
Abstract
The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
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Citations
26 Claims
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1. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array, and wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both.
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10. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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11. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays.
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12. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides.
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13. A memory device comprising:
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a plurality of memory arrays;
a plurality of row decoder circuits; and
a plurality of column decoder circuits;
wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides.
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Specification