Electronic devices with nonvolatile memory cells of reduced dimensions

• US 6,603,171 B2
• Filed: 08/20/2002
• Issued: 08/05/2003
• Est. Priority Date: 11/26/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Grossi, Alessandro, Clementi, Cesare
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US10/225,315
• Publication Number:
  US 20030064558A1
• Time in Patent Office: 350 Days
• Field of Search: 257/314, 257/326, 438/201, 438/257, 438/258, 438/266
• US Class Current: 257/326
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A process for the manufacturing of electronic devices, including memory cells, involving forming, on a substrate of semiconductor material, multilayer stacks including a floating gate region, an intermediate dielectric region, and a control gate region; forming a protective layer extending on top of the substrate and between the multilayer stacks and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks includes the step of defining the control gate region on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer isolates the multilayer stacks from each other at the sides. Word lines of metal extend above the protective layer and are in electrical contact with the gate regions.

Claims

1. An electronic device comprising:

a substrate of semiconductor material;

memory cells, each including a stack on top of said substrate;

each of said stacks comprising a floating gate region of semiconductor material, an intermediate dielectric region, and a control gate region of semiconductor material; and

a protective layer extending on top of said substrate and between said stack structures, said protective layer having a height at least equal to that of said stack structures; and

word lines of conductive material extending on top of said insulating material layer;

said control gate region is physically separated from control gate regions belonging to adjacent stack structures by said protective layer;

and said word lines extend on top of said control gate regions and are in electrical contact with said control gate regions.

2. The device of claim 1, comprising interconnection lines of metal, and said word lines comprise metal regions coplanar with said interconnection lines.

3. The device of claim 2, wherein said interconnection lines and said word lines are formed of tungsten.

4. The device of claim 1, wherein said stack structures extend on top of a first portion of said substrate and the device comprises diffused source and drain lines extending parallel to and alternating with one another, at a distance, in said substrate between rows of said stack structures, said diffused source and drain lines having one end that extends in a second portion of said substrate that is remote from said first portion and being electrically connected to source and drain contacts.

5. The device of claim 1, comprising first insulating regions and second insulating regions in a first area and, respectively, in a second area, separate from said first area, of a substrate of semiconductor material, wherein said first insulating regions are formed on top of said substrate and have a first height, and said second insulating regions are formed in trenches extending within said substrate and protrude from said trenches at a second height smaller than said first height.