Method of forming a multilayer dielectric stack

• US 6,627,503 B2
• Filed: 04/30/2002
• Issued: 09/30/2003
• Est. Priority Date: 02/11/2000
• Status: Expired due to Fees

• Current Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Laboratories of America Incorporated (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ma, Yanjun, Ono, Yoshi
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): BROPHY, JAMIE LYNN
• Application Number:
  US10/137,567
• Publication Number:
  US 20020130340A1
• Time in Patent Office: 518 Days
• Field of Search: 438/216, 438/261, 438/287, 438/761, 438/763, 438/778, 438/785
• US Class Current: 438/287
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Claims

1. A method of forming a dielectric stack comprising the steps of:

a) forming a first dielectric layer on an upper surface of a semiconductor substrate, wherein the first dielectric layer comprises a first dielectric material, which is HfO₂;

b) forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is selected from the group consisting of Al₂O₃, AlN, SiN, and Si₃N₄; and

c) forming a third dielectric layer above the second dielectric layer, wherein the third dielectric layer comprises the same dielectric material as the first dielectric material.

2. The method of claim 1, further comprising the step of annealing the semiconductor substrate at a temperature between approximately 400 and 900 degrees Celsius, whereby the dielectric stack is conditioned.

3. The method of claim 2, further comprising the step of depositing an electrode layer over the dielectric stack and the step of patterning the electrode layer and underlying dielectric stack to form a desired integrated circuit structure.

4. The method of claim 1, wherein the step of forming the first dielectric layer uses atomic layer deposition to deposit a layer of the first dielectric material.

5. The method of claim 4, wherein the step of forming the second dielectric layer uses atomic layer deposition to deposit a layer of the second dielectric material.

6. The method of claim 1, wherein the step of forming the first dielectric layer uses atomic layer deposition to deposit a first precursor of the first dielectric material.

7. The method of claim 6, further comprising the step of oxidizing the first precursor to form the first dielectric material.

8. The method of claim 6, wherein the first precursor is deposited as a self-limiting monolayer.

9. The method of claim 1, wherein the step of forming the first dielectric layer uses sputtering of a first target for a predetermined duration and the step of forming the second dielectric layer uses pulsed sputtering of a second target for a predetermined duration.

10. The method of claim 9, wherein the duration of sputtering the first target and the second target is controlled by shutters.

11. The method of claim 9, wherein sputtering is performed in an oxidizing atmosphere.

12. The method of claim 1, wherein the step of forming the first dielectric layer uses evaporation of a first target for a predetermined duration and the step of forming the second dielectric layer uses evaporation of a second target for a predetermined duration.

13. The method of claim 12, wherein the duration of evaporation of the first target and the second target is controlled by shutters.