Method and apparatus for a digital clock multiplication circuit

• US 6,661,298 B2
• Filed: 05/21/2002
• Issued: 12/09/2003
• Est. Priority Date: 04/25/2000
• Status: Expired due to Fees

• Current Assignee: National University of Singapore
• Original Assignee: National University of Singapore
• Inventors: Lye, Kin Mun, Joe, Jurianto
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US10/153,427
• Publication Number:
  US 20030006850A1
• Time in Patent Office: 567 Days
• Field of Search: 341/143, 341/111, 341/133, 377/47, 331/56, 331/53, 331/46, 331/49, 331/55, 327/116, 327/119, 327/113, 708/103
• US Class Current: 331/56
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68

Abstract

A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Claims

1. A frequency multiplication method comprising:

receiving an input signal, the input signal being cyclic, each cycle comprising a first half cycle and a second half cycle;

applying the input signal to a first circuit, the first circuit configured to produce a first plurality of pulses in response to a signal level of the first half cycle;

applying the input signal to a second circuit, the second circuit configured to produce a second plurality of pulses in response to a signal level of the second half cycle; and

combining the first plurality of pulses with the second plurality of pulses to produce an output signal that is representative of a frequency-multiplied version of the input signal, and wherein pulse widths of the first and second plurality of pulses depends on the signal level.

2. The method of claim 1 wherein the first plurality of pulses comprises n pulses and the second plurality of pulses comprises m pulses.

3. The method of claim 2 wherein n=m.

4. The method of claim 2 wherein n≠

m.

5. The method of claim 1 wherein the input signal is a square wave.

6. A frequency multiplication circuit comprising:

a circuit input for receiving an input signal, the input signal being cyclic, each cycle comprising a first half cycle and a second half cycle;

a first circuit portion having a first input coupled to receive at least the first half cycle of the input signal, the first circuit portion responsive to a signal level of the first half cycle by producing a first plurality of pulses;

a second circuit portion having a second input coupled to receive at least the second half cycle of the input signal, the second circuit portion responsive to a signal level of the second half cycle by producing a second plurality of pulses; and

a third circuit operable to combine the first and second plurality of pulses to produce an output signal and wherein pulse widths of the first and second plurality of pulses depend on the signal level.

7. The frequency multiplication circuit of claim 6 wherein the first and second circuit portions each is characterized by a transfer function having a stable operating region and an unstable operating region, wherein the first and second circuit portions each operates in the stable or unstable region depending on a signal level of the input signal, wherein the first and second circuit portions each produces pulses when operating in the unstable operating region and has a substantially non-oscillatory output when operating in the stable operating region.

8. The frequency multiplication circuit of claim 7 wherein the first and second circuit portions each operates in the unstable operating region in response to the input signal being at a first signal level and operates in the stable operating region in response to the input signal being at a second signal level, wherein the first half cycle is at the first signal level and the second half cycle is at the second signal level, wherein the second circuit portion includes a level shifting circuit to shift the signal level of the second half cycle to be at the first signal level.

9. The frequency multiplication circuit of claim 6 wherein the first plurality of pulses comprises n pulses and the second plurality of pulses comprises m pulses.

10. The frequency multiplication circuit of claim 6 wherein the first plurality of pulses comprises n pulses and the second plurality of pulses comprises m pulses, where n≠

m.

11. A frequency multiplication circuit comprising:

an input for receiving an input signal, the input signal being cyclic, each cycle comprising a first half cycle and a second half cycle;

first circuit means coupled to the input for producing first pulses in response to a signal level of first half cycles of the input signal;

second circuit means coupled to the input for producing second pulses in response to a signal level of second half cycles of the input signal; and

a combining means coupled to receive the first and second pulses for producing an output signal comprising the first and second pulses,

the first circuit means characterized by a transfer function having a stable operating region and an unstable operating region,

the second circuit means characterized by a transfer function having a stable operating region and an unstable operating region; and

wherein pulse widths of the first and second pulses depends on the signal level.