Switch matrix

• US 6,683,392 B2
• Filed: 08/20/2001
• Issued: 01/27/2004
• Est. Priority Date: 08/20/2001
• Status: Expired due to Fees

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Wu, Shih-Chang, Sorace, Ronald E., Reinhardt, Victor, Turley, Peter
• Primary Examiner(s): Sircus, Brian
• Assistant Examiner(s): DeBeradinis, Robert L.
• Application Number:
  US09/933,337
• Publication Number:
  US 20030038547A1
• Time in Patent Office: 890 Days
• Field of Search: 307/113, 307/147, 307/357, 385/17, 710/317
• US Class Current: 307/113
• CPC Class Codes: H04Q 2213/1302 Relay switches
• CPC Class Codes: H04Q 2213/1304 Coordinate switches, crossbar, 4/2 with relays, coupling field
• CPC Class Codes: H04Q 2213/13167 Redundant apparatus
• CPC Class Codes: H04Q 2213/13333 Earth satellites
• CPC Class Codes: H04Q 3/52 using static devices in switching stages, e.g. electronic switching arrangements

Abstract

A switch matrix 10 is provided comprising a plurality of input modules X and a plurality of output modules P. Each input module 16 has a plurality of first input interconnections 14, a plurality of first interconnected switches 21, and a plurality of first output interconnections 20. Each output module 18 has a plurality of second input interconnections 23, a plurality of second interconnected switches 24, and a plurality of second output interconnections 20. The plurality of input modules X is electrically coupled to the plurality of output modules P, forming a plurality of signal paths 12 having a plurality of interconnected switches K per signal path 12. A method is also provided minimizing the total number of interconnected switches Z within the switch matrix 10 for a particular application. The method comprises determining switch matrix design requirements, calculating the values of X and P, and performing an integer partitioning process.

Claims

1. A switch matrix comprising:

a plurality of first input interconnections (N);

a plurality of second output interconnections (M);

a plurality of input modules (X) wherein each input module comprises a group of input interconnections selected from said plurality of first input interconnections (N), a first plurality of interconnected switches, and a plurality of first output interconnections, wherein the sum of the input interconnections in said groups of input interconnections is equal to the total number of first input interconnections (N);

a plurality of output modules (P), wherein each output module comprises a plurality of second input interconnections, a second plurality of interconnected switches, and a group of output interconnections selected from said plurality of second output interconnections, wherein the sum of the output interconnections in said groups of output interconnections is equal to the total number of second output interconnections (M);

wherein said plurality of first output interconnections is electrically coupled to said plurality of second input interconnections;

wherein said plurality of input modules (X) are electrically coupled to said plurality of output modules (P), to form a plurality of signal paths having a plurality of interconnected switches (K) per signal path.

2. A system as in claim 1 wherein the number of output modules (P) is equal to the plurality of first input interconnections (N) divided by said plurality of input modules (X).

3. A system as in claim 1 wherein each input module (X) uses an equal number of input interconnections.

4. A system as in claim 1 wherein the number of input interconnections in each group of input interconnections is equal to the number of output modules (P).

5. A system as in claim 1 wherein each input module (X) is electrically coupled to all output modules (P).

6. A system as in claim 1 wherein each plurality of first output interconnections is equal to K*P.

7. A system as in claim 1 wherein the number of output interconnections in each output module is equal to said plurality of second output interconnections (M) divided by said plurality of output modules (P).

8. A system as in claim 1 wherein said first interconnected switches of each of said input modules (X) comprises switches selected from the group comprising:

field effect transistor switches, pin diode switches, piezoelectric switches, ferrite switches, and mechanical switches.

9. A system as in claim 1 wherein said second interconnected switches of each of said output modules (P) comprises switches selected from the group comprising:

field effect transistor switches, pin diode switches, piezoelectric switches, ferrite switches, and mechanical switches.

10. A system as in claim 1 wherein said plurality of input module (X) and said plurality of output module (P) are mounted on a plurality of respective circuit boards.

11. A system as in claim 1 wherein said first interconnected switches of each of said input modules (X) are bi-directional.

12. A system as in claim 1 wherein said second interconnected switches of each of said output modules (P) are bi-directional.

13. A system as in claim 1 wherein the values of said N, said M, said K, said P, K*P, K*N/P, N/P, and M/P are each an integer value.

14. A system as in claim 13 wherein the value of said P multiplied by the value of said K*P is an integer value.

15. A system as in claim 13 wherein the value of said K*N/P multiplied by the value of said M/P is an integer value.

16. A system as in claim 1 wherein each plurality of second input interconnections is equal to K*N/P.

17. A method of minimizing the total number of interconnected switches (Z) within a switch matrix having a plurality of first input interconnections (N), a plurality of input modules (X), a plurality of output modules (P), and a plurality of second output interconnections (M) comprising the steps of:

determining the values of P and X; and

performing an integer partitioning process.

18. A method according to claim 17 further comprising:

providing a desired degree of isolation;

providing a desired redundancy capability; and

providing a quantity of interconnected switches (K) per signal path as a function of said degree of isolation and said redundancy capability.

19. A method as in claim 17 wherein the step of determining the value of P comprises determining the value of P as a function of a constant value y and the value of M.

20. A method as in claim 17 wherein the step of determining the value of X comprises determining the value of X as a function of the values of N and P.

21. A method as in claim 17 wherein the step of calculating the value of X further comprises using a mathematical relationship, the value of N, and the value of P to calculate for X.

22. A method as in claim 17 wherein the step of performing integer partitioning comprises determining integer values for the quantity of:

interconnected switches, switch matrix interconnections, input modules, and output modules.