Integration of high voltage self-aligned MOS components
First Claim
1. In an CMOS or BiCMOS process a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, comprising the steps of:
- providing a semiconductor substrate;
forming n-well regions for the high voltage NMOS transistor and the low voltage PMOS transistor in the substrate by means of ion implantation;
forming a p-well region for the low voltage NMOS transistor in the substrate by means of ion implantation;
forming isolation areas on top of an/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage NMOS transistor;
producing gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;
depositing a layer of a conducting or semiconducting material thereon; and
patterning said layer to form the respective gate regions, whereby the gate region for the high voltage NMOS transistor is formed partly above the isolation area defining the voltage distributing region;
forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region;
forming source and drain regions for the low voltage PMOS transistors by means of creating ion implanted p+-regions; and
forming source and drain regions for the high voltage and low voltage NMOS transistors by means of creating ion implanted n+regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region, wherein;
the step of forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said p-doped channel region partly underneath the gate region of the high voltage NMOS transistor;
said isolation area defining said voltage-distributing region, said p-doped channel region, and said source and drain regions for the high voltage NMOS transistor are formed laterally within said n-well region for the high voltage NMOS transistor; and
a region extending in said n-well region for the high voltage NMOS transistors from said p-doped channel region to said drain for the high voltage-distributing region has a length, which is set by a length of said isolation area defining said voltage-distributing region and said step of forming a p-doped channel region for the high voltage NMOS transistors.
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Abstract
The invention relates to a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, in an n-well CMOS process by adding solely two additional process steps to a conventional CMOS process: (i) a masking step, and (ii) an ion implantation step for forming a doped channel region for the high voltage MOS transistor in the substrate self-aligned to the edge of the high voltage MOS transistor gate region. The ion implantation is performed through the mask in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create the doped channel region partly underneath the gate region of the high voltage MOS transistor.
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Citations
29 Claims
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1. In an CMOS or BiCMOS process a method for forming a high voltage NMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, comprising the steps of:
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providing a semiconductor substrate;
forming n-well regions for the high voltage NMOS transistor and the low voltage PMOS transistor in the substrate by means of ion implantation;
forming a p-well region for the low voltage NMOS transistor in the substrate by means of ion implantation;
forming isolation areas on top of an/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage NMOS transistor;
producing gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;
depositing a layer of a conducting or semiconducting material thereon; and
patterning said layer to form the respective gate regions, whereby the gate region for the high voltage NMOS transistor is formed partly above the isolation area defining the voltage distributing region;
forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region;
forming source and drain regions for the low voltage PMOS transistors by means of creating ion implanted p+-regions; and
forming source and drain regions for the high voltage and low voltage NMOS transistors by means of creating ion implanted n+regions, wherein the source region for the high voltage NMOS transistor is created within the p-doped channel region, wherein;
the step of forming a p-doped channel region for the high voltage NMOS transistor in the substrate self-aligned to the edge of the high voltage NMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said p-doped channel region partly underneath the gate region of the high voltage NMOS transistor;
said isolation area defining said voltage-distributing region, said p-doped channel region, and said source and drain regions for the high voltage NMOS transistor are formed laterally within said n-well region for the high voltage NMOS transistor; and
a region extending in said n-well region for the high voltage NMOS transistors from said p-doped channel region to said drain for the high voltage-distributing region has a length, which is set by a length of said isolation area defining said voltage-distributing region and said step of forming a p-doped channel region for the high voltage NMOS transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 24, 25, 26)
a p-well region for the high voltage PMOS transistor is formed in the substrate simultaneously with the formation of the p-well region for the low voltage NMOS transistor; an isolation area defining a voltage-distributing region in the high voltage PMOS transistor is formed simultaneously with the formation of said isolation areas;
a gate region for the high voltage PMOS transistor is produced simultaneously as the production of said gate regions for the high voltage NMOS transistor and the low voltage NMOS and PMOS transistors, respectively, whereby the gate region for the high voltage PMOS transistor is formed partly above the isolation area defining the voltage distributing region in the high voltage PMOS transistor; and
further comprising;
forming an n-doped channel region for the high voltage PMOS transistor in the substrate self-aligned to the edge of the high voltage PMOS transistor gate region, by means of ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said n-doped channel region partly underneath the gate region of the high voltage PMOS transistor; and
forming drain and source regions for the high voltage PMOS transistor by means of creating ion implanted p+regions.
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19. The method as claimed in claim 18 wherein the step of forming a p-well region for the high voltage PMOS transistor is preceded by the formation of a large n-doped region for the high voltage PMOS transistor;
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wherein the p-well region for the high voltage PMOS transistor is formed within said n-doped region.
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20. An integrated CMOS- or BiCMOS-based circuit comprising at least a high voltage NMOS transistor, a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, wherein said transistors are formed according to the method as claimed in claim 1.
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24. The method as claimed in claim 1 wherein the respective transistors are high frequency transistors.
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25. The method as claimed in claim 1 wherein the respective transistors are radio frequency transistors.
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26. The method as claimed in claim 1 wherein said ion implantation is effectuated to set the doping profile of said p-doped channel region without the use of a diffusion step.
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21. In an CMOS or BiCMOS process a method for forming a high voltage PMOS transistor together with a low voltage NMOS transistor and a low voltage PMOS transistor, respectively, comprising the steps of:
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providing a semiconductor substrate;
forming an n-well region for the low voltage PMOS transistor in the substrate by means of ion implantation;
forming p-well regions for the high voltage PMOS transistors and the low voltage NMOS transistor in the substrate by means of ion implantation;
forming isolation areas on top of and/or in the substrate to laterally separate the transistors from each other and to define a voltage-distributing region in the high voltage PMOS transistor;
producing gate regions for the high voltage PMOS transistor and the low voltage NMOS and PMOS transistors, respectively, by forming a respective thin gate oxide on the substrate;
depositing a layer of a conducting or a semiconducting material thereon; and
patterning said layer to form the respective gate regions, whereby the gate region for the high voltage PMOS transistor is formed partly above the isolation area defining the voltage distributing region;
forming an n-doped channel region for the high voltage PMOS transistor in the substrate self-aligned to the edge of the high voltage PMOS transistor gate region;
forming drain and source regions for the high and low voltage PMOS transistors by means of creating ion implanted p+-regions, wherein the source region for the high voltage PMOS transistor is created within the n-doped channel region;
forming drain and source regions for the low voltage NMOS transistor by means of creating ion implanted n+-well regions, wherein;
the step of forming an n-doped channel region for the high voltage PMOS transistor in the substrate self-aligned to the edge of the high voltage PMOS transistor gate region is performed by ion implantation through a mask, said ion implantation being effectuated in a direction, which is inclined at an angle to the normal of the substrate surface, to thereby create said n-doped channel region partly underneath the gate region of the high voltage PMOS transistor;
said isolation area defining said voltage-distributing region, said p-doped channel region, and said source and drain regions for the high voltage NMOS transistor are formed laterally within said n-well region for the high voltage NMOS transistor; and
a region extending in said n-well region for the high voltage NMOS transistors from said p-doped channel region to said drain for the high voltage-distributing region has a length, which is set by a length of said isolation area defining said voltage-distributing region and said step of forming a p-doped channel region for the high voltage NMOS transistors. - View Dependent Claims (22, 23, 27, 28, 29)
said transistors are formed according to the method as claimed in claim 21. -
27. The method as claimed in claim 21 wherein the respective transistors are high frequency transistors.
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28. The method as claimed in claim 21 wherein the respective transistors are radio frequency transistors.
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29. The method as claimed in claim 21 wherein said ion implantation is effectuated to set the doping profile of said p-doped channel region without the use of a diffusion step.
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Specification