Power MOS element and method for producing the same

• US 6,693,011 B2
• Filed: 08/21/2002
• Issued: 02/17/2004
• Est. Priority Date: 10/02/2001
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Wahl, Uwe, Vogt, Holger
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Brock II, Paul E
• Application Number:
  US10/225,022
• Publication Number:
  US 20030001215A1
• Time in Patent Office: 545 Days
• Field of Search: 438/270, 438/271, 438/137, 438/138, 438/156, 438/173, 438/192, 438/206, 438/209, 438/212, 438/268
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region. Furthermore, said power MOS element includes a plurality of basically parallel gate trenches which extend to said drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in said connecting gate trench. For producing, three photolithographic steps are sufficient, which serve to etch said gate trenches and said connecting gate trench, to produce said contact holes for said source region and said channel region as well as for said connecting gate trench, and to finally structure said gate contacts and said source contact. Thus, a flexible layout concept is possible in which said gate contact can also be placed in the middle of or at another location on said power MOS element without additional expenditure. Optionally, without additional process steps, margin terminating structures can be produced parallel to the formation of said active transistor region in the form of circumferential floating rings or of floating field plates.

Claims

1. Method for producing a power MOS element, comprising the following steps:

providing a substrate having a drift region with a doping of a first doping type, a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type and said channel region bordering on said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region;

photolithographic producing of essentially parallel gate trenches spaced from one another defining an active region of the power MOS element, and of a connecting gate trench by means of which said plurality of essentially parallel gate trenches is connectable to one another in an electrically conductive way in such a way that said gate trenches extend through said source region, said channel region and into said drift region,

wherein said connecting gate trench being a circumferential trench comprising a first connecting region, a second connecting region, a first longitudinal region and a second longitudinal region, said first connecting region connecting first ends of said plurality of gate trenches to one another, said second connecting gate trench connecting second ends of said plurality of gate trenches to one another, and said first and said second longitudinal regions connecting said first and said second connecting regions to one another in such a way that the active region which is defined by said plurality of gate trenches is completely surrounded by said connecting gate trench;

or

wherein said connecting gate trench comprising a circumferential section surrounding a non-active region of said power MOS element, in which there are no gate trenches, and extension sections being connected to said circumferential section in an electrically conductive way, said extension sections connecting at least a part of said gate trenches to one another in an electrically conductive way;

processing said gate trenches and said connecting gate trench in order to comprise a conductive material which is isolated from said source region, said channel region and said drift region by an insulator;

photolithographic producing of contact holes for contacting said source region, said channel region and said connecting gate trench, said connecting gate trench being contactable via said contact holes associated to said connecting gate trench;

filling said contact holes with an electrically conductive material; and

photolithographic producing of said gate contact, said source contact and said channel contact.

2. Method according to claim 1 wherein the steps of photolithographic producing each comprise a step of producing a mask and a step of etching to a specific depth.

3. Method according to claim 1 wherein the step of providing comprises the following steps:

implanting a channel region into a semiconductor substrate which is doped with said first doping type; and

implanting said source region into said semiconductor substrate.

4. Method according to claim 1 wherein the step of is providing a substrate comprises the following steps:

epitaxial growing of said channel region onto a semiconductor substrate;

implanting said source region into said epitaxially grown channel region.

5. Method according to claim 1 wherein, after the step of the photolithographic producing of said gate trenches and said connecting gate trench, at least one purification oxidation with subsequent removal of said purification oxide is carried out.

6. Method according to claim 1 wherein the step of processing said gate trenches and said connecting gate trench comprises the following steps:

carrying out a gate oxidation to produce said insulator;

filling said oxidized trenches with said conductive material;

removing conductive material in such a way that only said conductive material remains in said trenches; and

depositing an intermediate oxide.

7. Method according to claim 6 wherein said intermediate oxide comprises doped or undoped CVC-oxides, such as boron phosphorus silicate glass or silane oxide or combinations of oxide and nitride.

8. Method according to claim 1 wherein, in the step of photolithographic producing and of processing said gate trenches and said connecting gate trench, at least one terminating trench is produced which surrounds an active region of said power MOS element, the active region being established by said plurality of gate trenches and said connecting gate trench.

9. Method according to claim 1 wherein, after the photolithographic producing of said contact holes, a contact hole implantation is carried out to enable a low-resistance contact to said channel region.

10. Method according to claim 1 wherein, after the step of the photolithographic producing of said contact holes, a further contact hole implantation is carried out to modify the doping profile of said channel region and said drift region.

11. Method according to claim 1 wherein said contact holes are filled with a conductive material, whereby said source region and said channel region are short-circuited and said connecting gate trench is contacted.

12. Method according to claim 1 wherein, prior to the photolithographic producing of said gate contact, said source and said channel contacts, a full area metal layer comprising tungsten, aluminium or a combination of tungsten and aluminium is deposited.

13. Method according to claim 1 wherein, in the step of the photolithographic producing of said gate contact, said source contact and said channel contact, a source contact is produced which essentially extends over the whole surface of said power MOS element, except for a region around said connecting gate in which said gate contact is located.

14. Method according to claim 8 wherein, in the step of the photolithographic producing and processing of said gate trenches and said connecting gate trench, a plurality of terminating trenches which are not contacted and whose mutual distance increases towards the margin of said power MOS element is formed.

15. Method according to claim 8 wherein said terminating trench has a width which is 5 to 25 times as big as the width of a gate trench, and wherein, in the step of the photolithographic producing of said contact holes, a contact hole is produced in said source region and said channel region next to said terminating trench and in an electrically conductive material at the margin of said terminating trench, and wherein, in the step of the photolithographic producing of said gate contacts, said source contact and said channel contact, a metallic connection between said contact hole in said terminating trench and said contact hole in said source region and said channel region is produced to produce a field-plate-like structure.

16. Method according to claim 13 wherein said connecting gate trench, said source contact and said gate contact are arranged in such a way that said gate contact is essentially located in the middle of said power MOS element.

17. Method according to claim 1 wherein the step of processing said gate trenches comprises the following substeps:

producing a gate oxide in said gate trenches;

depositing a layer of polysilicon onto said gate oxide;

depositing tungsten onto said polysilicon;

thermal treating of said arrangement in such a way that a silicidation takes place.

18. Method according to claim 1

wherein the step of providing comprises the following steps:

implanting a channel region into a semiconductor substrate which is doped with a first doping type; and

implanting said source region into said semiconductor substrate;

and which, after the step of the photolithographic producing of said gate contact, said source contact and said channel contact, further comprises the following steps;

grinding back said semiconductor substrate on that side which is opposite to the side in which said gate trenches are formed;

implanting a highly doped region into said semiconductor substrate from that side which is ground back; and

depositing a rear side metalization to produce a drain contact.