Method of manufacturing semiconductor device having trench filled up with gate electrode

• US 6,696,323 B2
• Filed: 01/13/2003
• Issued: 02/24/2004
• Est. Priority Date: 10/19/1999
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Shibata, Takumi, Yamaguchi, Hitoshi, Sakakibara, Jun, Morishita, Toshiyuki, Sakakibara, Toshio
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US10/340,746
• Publication Number:
  US 20030141514A1
• Time in Patent Office: 407 Days
• Field of Search: 438/133, 438/137, 438/138, 438/212, 438/270, 438/271, 438/272, 438/589
• US Class Current: 438/138
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66378 the other device being a controlling field-effect device
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 : with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In a semiconductor device, a p-type base region is provided in an n⁻-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n⁺-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n⁺-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n⁺-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

Claims

1. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a second conductivity type base region by filling up the first trench with a second conductivity type semiconductor;

forming a second trench within the base region and a third trench in the semiconductor substrate at a location remote from the base region, each of the second trench and the third trench extending from the principal surface in the perpendicular direction;

forming a first conductivity type source region by filling up the second trench with a first conductivity type semiconductor, and forming a first conductivity type drain region by filling up the third trench with the first conductivity type semiconductor;

forming a fourth trench penetrating the base region from the source region, the fourth trench extending form the principal surface in the perpendicular direction;

forming a gate insulating film in the fourth trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

2. A method for manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

forming a first trench at a first region of the semiconductor substrate and a second trench at a second region of the semiconductor substrate remote from the first region, each of the first trench and the second trench extending in the semiconductor substrate form the principal surface in a perpendicular direction with respect to the principal surface;

covering the principal surface of the semiconductor substrate with a mask exposing the first trench from an opening of the mask while covering the second trench;

forming a second conductivity type base region in the first trench by diffusing a second conductivity type impurity into the semiconductor substrate from the first trench, through the mask;

removing the mask;

forming a first conductivity type source region by filling up the first trench with a first conductivity type semiconductor, and forming a first conductivity type drain region by filling up the second trench with the first conductivity type semiconductor;

forming a third trench in the semiconductor substrate to penetrate the base region from the source region and to extend from the principal surface in the perpendicular direction;

forming a gate insulating film in the third trench;

forming a gate electrode on the gate insulating film to fill up the third trench;

forming a source electrode electrically connected to the source region and the base region; and

forming a drain electrode electrically connected to the drain region.

3. A method for manufacturing a semiconductor device, comprising:

preparing a semiconductor substrate having a principal surface and a back surface being an opposite surface of the principal surface;

forming a first trench at a first region of the semiconductor substrate and a second trench at a second region of the semiconductor substrate remote from the first region, each of the first trench and the second trench extending in the semiconductor substrate form the principal surface in a perpendicular direction with respect to the principal surface;

covering the principal surface of the semiconductor substrate with a mask exposing the second trench from an opening of the mask while covering the first trench;

forming a first conductivity type drift region in the semiconductor substrate by diffusing a first conductivity type impurity into the semiconductor substrate from the second trench, through the mask;

removing the mask;

forming a first conductivity type source region by filling up the first trench with a first conductivity type semiconductor, and forming a first conductivity type drain region by filling up the second trench with the first conductivity type semiconductor;

forming a third trench in the semiconductor substrate to penetrate the base region from the source region and to extend from the principal surface in the perpendicular direction;

forming a gate insulating film in the third trench;

forming a gate electrode on the gate insulating film to fill up the third trench;

forming a source electrode electrically connected to the source region and the base region; and

forming a drain electrode electrically connected to the drain region.

4. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift formation film constituting a first conductivity type drift region, in the first trench such that the drift formation film covers an inner wall of the first trench and has a recess;

forming a base formation film constituting a second conductivity type base region in the recess of the drift formation film such that the base formation film covers the drift region in the trench and has a recess;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the drift formation film, the base formation film, and the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

8. The method according to any one of claims 4 to 7, wherein the semiconductor substrate is a (110) substrate.

9. The method according to any one of claims 4 to 7, further comprising:

forming a third trench in one of the source region and the drain region, the third trench extending from the principal surface of the semiconductor substrate in the perpendicular direction; and

forming a resistance lowering layer in the third trench.

5. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift formation film constituting a first conductivity type drift region, in the first trench such that the drift formation film covers an inner wall of the first trench and has a recess;

forming a second conductivity type base region at a surface portion of the drift region by doping a second conductivity type impurity into the surface portion of the drift region in the trench;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the drift formation film and the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region base and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

6. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift region by doping a second conductivity type impurity into the semiconductor substrate from an inner wall of the first trench;

forming a base region in the drift region by doping the second conductivity type impurity from the inner wall of the first trench;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region base and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.

7. A method for manufacturing a semiconductor device, comprising:

preparing a first conductivity type semiconductor substrate having a principal surface and a back surface at an opposite side of the principal surface;

forming a first trench in the semiconductor substrate, the first trench extending in the semiconductor substrate from the principal surface in a perpendicular direction with respect to the principal surface;

forming a drift region by doping a second conductivity type impurity into the semiconductor substrate from an inner wall of the first trench;

forming a base formation film constituting a second conductivity base region, the base formation film covering the drift region in the first trench and having a recess corresponding to the first trench;

forming a source formation film constituting a first conductivity type source region such that the source formation film covers the base region in the trench;

flattening the base formation film and the source formation film;

forming a second trench in the semiconductor substrate, the second trench passing through the base region from the source region base and extending from the principal surface in the perpendicular direction;

forming a gate insulating film in the second trench;

forming a gate electrode on a surface of the gate insulating film;

forming a source electrode electrically connected to the source region and the base region; and

forming drain electrode electrically connected to the drain region.