Memory device and method for temperature-based control over write and/or read operations
First Claim
1. A method for temperature-based control over a write operation to a memory array, the method comprising:
- (a) monitoring temperature of a memory array of a memory device; and
(b) preventing a write operation to the memory array in response to the monitored temperature reaching a threshold temperature;
wherein (b) is performed by at least one component in the memory device, wherein the memory device comprises a housing, and wherein the memory array and the at least one component are located within the housing.
8 Assignments
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Accused Products
Abstract
The preferred embodiments described herein provide a memory device and method for temperature-based control over write and/or read operations. In one preferred embodiment, the temperature of a memory array is monitored, and a write operation to the memory array is prevented in response to the monitored temperature reaching a threshold temperature. In another preferred embodiment, the temperature of a memory array is monitored, and a read operation from the memory array is prevented in response to the monitored temperature reaching a threshold temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
123 Citations
72 Claims
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1. A method for temperature-based control over a write operation to a memory array, the method comprising:
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(a) monitoring temperature of a memory array of a memory device; and
(b) preventing a write operation to the memory array in response to the monitored temperature reaching a threshold temperature;
wherein (b) is performed by at least one component in the memory device, wherein the memory device comprises a housing, and wherein the memory array and the at least one component are located within the housing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 42, 43)
(c) allowing the write operation to be performed to the memory array in response to the monitored temperature being below the threshold temperature.
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9. The invention of claim 8, wherein the act of preventing a write operation in (b) comprises preventing a start of a new write operation, and wherein the act of allowing the write operation to be performed in (c) comprises allowing the start of the new write operation.
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10. The invention of claim 8, wherein the act of preventing a write operation in (b) comprises allowing an in-progress write operation to end and preventing a start of a new write operation, and wherein the act of allowing the write operation to be performed in (c) comprises allowing the start of the new write operation.
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11. The invention of claim 8, wherein the act of preventing a write operation in (b) comprises interrupting an in-progress write operation, and wherein the act of allowing the write operation to be performed in (c) comprises resuming the in-progress write operation.
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12. The invention of claim 1 further comprising:
(c) preventing a read operation from the memory array in response to the monitored temperature reaching a second threshold temperature.
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13. The invention of claim 1, wherein the temperature is monitored in (a) with a first temperature sensor, and wherein the invention further comprises:
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monitoring temperature of the memory array with a second temperature sensor; and
preventing a read operation from the memory array in response to the monitored temperature from the second temperature sensor reaching a second threshold temperature.
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14. The invention of claim 1, wherein the memory array comprises a three-dimensional memory array.
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15. The invention of claim 1, wherein the memory array comprises a plurality of antifuse memory cells.
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16. The invention of claim 1, wherein the memory array comprises a plurality of write-once memory cells.
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17. The invention of claim 1, wherein the memory array comprises a plurality of write-many memory cells.
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42. The invention of claim 1, 18, or 35, wherein the threshold temperature comprises a thermal run-away temperature of the memory array.
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43. The invention of claim 1, 18, or 35, wherein the threshold temperature comprises a temperature greater than a thermal run-away temperature of the memory array.
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18. A method for temperature-based control over a read operation from a memory array, the method comprising:
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(a) monitoring temperature of a memory array of a memory device; and
(b) preventing a read operation from the memory array in response to the monitored temperature reaching a threshold temperature;
wherein (b) is performed by at least one component in the memory device, wherein the memory device comprises a housing, and wherein the memory array and the at least one component are located within the housing. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
(c) allowing the read operation to be performed to the memory array in response to the monitored temperature being below the threshold temperature.
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26. The invention of claim 25, wherein the act of preventing a read operation in (b) comprises preventing a start of a new read operation, and wherein the act of allowing the read operation to be performed in (c) comprises allowing the start of the new read operation.
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27. The invention of claim 25, wherein the act of preventing a read operation in (b) comprises allowing an in-progress read operation to end and preventing a start of a new read operation, and wherein the act of allowing the read operation to be performed in (c) comprises allowing the start of the new read operation.
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28. The invention of claim 25, wherein the act of preventing a read operation in (b) comprises interrupting an in-progress read operation, and wherein the act of allowing the read operation to be performed in (c) comprises resuming the in-progress read operation.
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29. The invention of claim 18 comprising:
(c) preventing a write operation to the memory array in response to the monitored temperature reaching a second threshold temperature.
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30. The invention of claim 18, wherein the temperature is monitored in (a) with a first temperature sensor, and wherein the invention further comprises:
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monitoring temperature of the memory array with a second temperature sensor; and
preventing a write operation to the memory array in response to the monitored temperature from the second temperature sensor reaching a second threshold temperature.
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31. The invention of claim 18, wherein the memory array comprises a three-dimensional memory array.
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32. The invention of claim 18, wherein the memory array comprises a plurality of antifuse memory cells.
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33. The invention of claim 18, wherein the memory array comprises a plurality of write-once memory cells.
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34. The invention of claim 18, wherein the memory array comprises a plurality of write-many memory cells.
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35. A memory device comprising:
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a memory array;
a temperature sensor; and
write operation control circuitry coupled with the memory array and the temperature sensor and operative to prevent a write operation to the memory array in response to a temperature sensed by the temperature sensor reaching a threshold temperature;
wherein the memory device comprises a housing, and wherein the memory array, the temperature sensor, and the write operation control circuitry are located within the housing. - View Dependent Claims (36, 37, 38, 39, 40, 41)
a comparator operative to compare an output of the temperature sensor to a reference voltage;
a pulse signal generator coupled with the comparator and operative to generate a pulse signal with voltage hysteresis; and
an edge triggered flip flop coupled with the pulse signal generator.
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41. The invention of claim 35, wherein the memory array comprises a plurality of antifuse memory cells.
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44. A memory device comprising:
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a memory array;
a temperature sensor; and
write operation control circuitry coupled with the memory array and the temperature sensor and operative to prevent a write operation to the memory array in response to a temperature sensed by the temperature sensor reaching a threshold temperature;
wherein the memory array comprises a three-dimensional memory array. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54)
a comparator operative to compare an output of the temperature sensor to a reference voltage;
a pulse signal generator coupled with the comparator and operative to generate a pulse signal with voltage hysteresis; and
an edge triggered flip flop coupled with the pulse signal generator.
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50. The invention of claim 44, wherein the memory array comprises a plurality of antifuse memory cells.
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51. The invention of claim 44, wherein the memory array comprises a plurality of write-once memory cells.
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52. The invention of claim 44, wherein the memory array comprises a plurality of write-many memory cells.
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53. The invention of claim 44, wherein the threshold temperature comprises a thermal run-away temperature of the memory array.
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54. The invention of claim 44, wherein the threshold temperature comprises a temperature greater than a thermal run-away temperature of the memory array.
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55. A memory device comprising:
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a memory array;
a temperature sensor; and
write operation control circuitry coupled with the memory array and the temperature sensor and operative to prevent a write operation to the memory array in response to a temperature sensed by the temperature sensor reaching a threshold temperature;
wherein the memory array comprises a plurality of write-once memory cells. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63)
a comparator operative to compare an output of the temperature sensor to a reference voltage;
a pulse signal generator coupled with the comparator and operative to generate a pulse signal with voltage hysteresis; and
an edge triggered flip flop coupled with the pulse signal generator.
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61. The invention of claim 55, wherein the memory array comprises a plurality of antifuse memory cells.
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62. The invention of claim 55, wherein the threshold temperature comprises a thermal run-away temperature of the memory array.
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63. The invention of claim 55, wherein the threshold temperature comprises a temperature greater than a thermal run-away temperature of the memory array.
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64. A memory device comprising:
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a memory array;
a temperature sensor; and
write operation control circuitry coupled with the memory array and the temperature sensor and operative to prevent a write operation to the memory array in response to a temperature sensed by the temperature sensor reaching a threshold temperature;
wherein the memory array comprises a plurality of write-many memory cells. - View Dependent Claims (65, 66, 67, 68, 69, 70, 71, 72)
a comparator operative to compare an output of the temperature sensor to a reference voltage;
a pulse signal generator coupled with the comparator and operative to generate a pulse signal with voltage hysteresis; and
an edge triggered flip flop coupled with the pulse signal generator.
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70. The invention of claim 64, wherein the memory array comprises a plurality of antifuse memory cells.
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71. The invention of claim 64, wherein the threshold temperature comprises a thermal run-away temperature of the memory array.
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72. The invention of claim 64, wherein the threshold temperature comprises a temperature greater than a thermal run-away temperature of the memory array.
Specification