Circuits and methods using vertical, complementary transistors

• US 6,777,744 B2
• Filed: 06/04/2001
• Issued: 08/17/2004
• Est. Priority Date: 02/24/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/873,650
• Publication Number:
  US 20010025985A1
• Time in Patent Office: 1,170 Days
• Field of Search: 438/199, 438/200, 438/212, 257/329, 257/330, 257/331, 257/332, 257/333, 257/350, 257/351, 257/374
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method and structure for an improved, vertically configured inverter array is provided. The inverter includes a buried gate contact coupling the body regions of a complementary pair of transistors. An electrical contact couples the second source/drain regions of the complementary pair of transistors. The transistors are formed in vertical pillars of single crystalline semiconductor material.

Claims

1. An inverter, comprising:

a first vertically configured transistor formed within a first vertically configured structure extending outwardly from, a semiconductor substrate;

a second vertically configured transistor formed within a second vertically configured structure extending outwardly from a semiconductor substrate;

an electrical contact between source/drain regions of the first and second vertically configured transistors to provide an output for the inverter; and

a shared gate contact located adjacent to the body regions of the first and the second vertically configured transistors, the shared gate contact interconnecting the vertically configured transistors wherein the gate contact comprises an input to the inverter.

2. A method of fabricating an inverter, comprising:

forming a first vertically configured transistor, the first transistor extending outwardly from a semiconductor substrate;

forming a second vertically configured transistor, the second transistor extending outwardly from a semiconductor substrate;

forming an electrical contact between source/drain regions of the first and second vertically configured transistors to provide an output for the inverter; and

forming a single gate contact, the gate contact located adjacent to the body regions of the first and second vertically configured transistors wherein the gate contact comprises an input to the inverter.

3. The method of fabricating an inverter of claim 2, wherein forming the first vertically configured transistor comprises forming a first transistor having a number of sides, the first transistor having a body region of a first conductivity type and first and second source/drain regions, the first transistor further having a gate that is associated with a side of the first transistor.

4. The method of fabricating an inverter of claim 3, wherein forming the second vertically configured transistor comprises forming a second transistor having a number of sides, the second transistor having a body region of a second conductivity type and first and second source/drain regions, the second transistor further having a gate that is associated with a side of the second transistor.

5. The method of fabricating an inverter of claim 4, wherein forming a gate contact comprises forming a gate contact that interconnects the gates of the first and second transistors.

6. The method of fabricating an inverter of claim 5, wherein forming the electrical contact between the first and second transistor types comprises forming a tungsten shunt that interconnects a second source/drain region of the first transistor with a second source/drain region of the second transistor.

7. A method of fabricating an inverter, comprising:

forming a first transistor in a first pillar of single crystalline semiconductor material that extends outwardly from the substrate, the first pillar having a number of sides, the first transistor having a body region and first and second source/drain regions that are vertically aligned, the first transistor further having a gate that is associated with a side of the first transistor and adjacent to the body region of the first transistor;

forming a second transistor in a second pillar of single crystalline semiconductor material that extends outwardly from the substrate, the second pillar having a number of sides, the second transistor having a body region and first and second source/drain regions that are vertically aligned, the second transistor further having a gate that is associated with a side of the second transistor and adjacent to the body region of the second transistor

forming a single, shared gate contact located adjacent to the gates and the the body regions of both first and second transistors; and

forming a metal contact between the first source/drain regions of the first and second transistor types.

8. The method of fabricating an inverter of claim 7, wherein forming the first includes forming a first source/drain region of a first conductivity.

9. The method of fabricating an inverter of claim 7, wherein forming the first transistor includes forming a first source/drain region of a second conductivity type.

10. The method of fabricating an inverter of claim 7, wherein forming the first and second transistors includes forming the first source/drain region of the first and second transistors on oppositely doped semiconductor material.

11. The method of fabricating an inverter of claim 7, wherein forming first and second transistors comprises selectively growing multiple epitaxial layers of differently doped silicon.

12. A method of fabricating an array of inverters, comprising:

forming multiple complementary pairs of transistors extending outwardly from a semiconductor substrate and having upper surfaces, each transistor in a pair having a vertically stacked body region and a first and second source/drain regions, each transistor further having a gate;

forming an electrical contact between the transistors in each complementary pair;

forming a plurality of isolation trenches extending parallel to and between the multiple complementary pairs of transistors; and

forming a shared gate contact adjacent to the slates and the body regions in each complementary pair of transistors, and wherein the gate contact communicates with the body region of each transistor in the pair.

13. The method of fabricating an array of claim 12, wherein forming the electrical contact comprises coupling the second source/drain region of the transistors in each pair.

14. The method of fabricating an array of claim 12, and comprising interconnecting electrical contacts and gate contacts of selected pairs so that the array of inverters implements a logical function.

15. The method of fabricating an array of claim 12, wherein forming a gate contact further includes forming an electrical input, connected to the gate contact, and adapted to receive electrical input from both external sources as well as other ones of the multiple complementary pairs of transistors.

16. The method of fabricating an array of claim 12, wherein forming the gate contact comprises forming the gate contact below the upper surface of the multiple complementary pairs of transistors.

17. The method of fabricating an array of claim 12, wherein forming the multiple complementary pairs of transistors includes forming each transistor in a pair of complementary transistors having oppositely doped regions in each of the pillars.

18. The method of fabricating an array of claim 12, wherein forming multiple complementary pairs of transistors comprises selectively growing multiple epitaxial layers of differently doped silicon.

19. The method of fabricating an array of claim 12, wherein forming a plurality of isolation trenches comprises selectively etching an orthogonally bisecting pattern parallel to and between the multiple complementary pairs of transistors.

20. A method of fabricating an array, comprising:

forming alternating first source/drain region layers of differently doped semiconductor material extending outwardly from a semiconductor substrate;

forming alternating body region layers of differently doped semiconductor material on the first source/drain region layer;

forming alternating second source/drain region layers of differently doped semiconductor material on the body region layers;

forming a plurality of isolation trenches so as to form isolated pillars of semiconductor material, each including a first source/drain region, a body region and a second source/drain region for a transistor;

forming a gate contact disposed within at least one of the plurality of trenches, wherein the gate contact couples body regions of a complementary pair of transistors; and

connecting the second source/drain regions of the complementary transistors to form an inverter.

21. A method of fabricating an array of inverters, comprising:

implanting ions into a semiconductor substrate in an alternating parallel pattern so as to form alternating bars of differently doped semiconductor material;

selectively growing, upon the alternating bars, multiple epitaxial layers of differently doped silicon in order to create an alternating parallel pattern of differently doped vertically configured silicon material;

forming a plurality of orthogonally bisecting isolation trenches to form a pattern of differently doped vertically configured silicon pillars;

forming electrical contacts between complementary pairs of the differently doped vertically configured silicon pillars; and

forming gate contacts within at least one of the plurality of orthogonally bisecting isolation trenches that interconnects complementary pairs of differently doped vertically configured silicon pillars.