Semiconductor die package including drain clip

• US 6,777,800 B2
• Filed: 09/30/2002
• Issued: 08/17/2004
• Est. Priority Date: 09/30/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Quinones, Maria Clemens Y., Madrid, Ruben
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US10/262,170
• Publication Number:
  US 20040063240A1
• Time in Patent Office: 687 Days
• Field of Search: 257/666, 257/690, 257/693, 257/735, 257/778, 257/779, 257/678, 438/106, 438/112, 438/127, 438/611, 438/612, 438/123
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/37147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/84 using a strap connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor die package including a semiconductor die including a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive molding material encapsulates the semiconductor die. The major surface of the drain clip is exposed through the non-conductive molding material.

Claims

1. A semiconductor die package comprising:

(a) a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface, and a drain region at the second surface;

(b) a drain clip having a major surface and being electrically coupled to the drain region;

(c) a gate lead electrically coupled to the gate region;

(d) a source lead electrically coupled to the source region; and

(e) a non-conductive molding material encapsulating the semiconductor die, wherein the major surface of the drain clip is exposed through the non-conductive molding material,

wherein the molding material has a ton surface and a bottom surface, wherein the top surface is substantially coplanar with the major surface of the drain din and wherein the bottom surface is substantially coplanar with a surface of the sate lead and a surface of the source lead.

2. The semiconductor die package of claim 1 further comprising a drain lead electrically coupled to an end of the drain clip, wherein at least a surface of the drain lead is substantially coplanar with a surface of the gate lead and a surface of the source lead.

3. The package of claim 1 wherein the drain clip comprises copper.

4. A semiconductor die package comprising:

(a) a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface, and a drain region at the second surface;

(b) a drain din having a major surface and being electrically coupled to the drain region;

(c) a gate lead electrically coupled to the gate region;

(d) a source lead electrically coupled to the source region; and

(e) a non-conductive molding material encapsulating the semiconductor die, wherein the major surface of the drain clip is exposed through the non-conductive molding material, and wherein the package includes a source lead structure, and wherein the source lead structure includes a die attach pad, and wherein the semiconductor die is attached to the die attach pad.

5. A semiconductor die package comprising:

(a) a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface; and

a drain region at the second surface;

(b) a drain clip having a major surface and being electrically coupled to the drain region;

(c) a gate lead electrically coupled to the gate region;

(d) a source lead electrically coupled to the source region; and

(e) a non-conductive molding material encapsulating the semiconductor die, wherein the major surface of the drain clip is exposed through the non-conductive molding material, wherein the source lead is part of a source lead structure having a major surface, and wherein the molding material has a top surface and a bottom surface, wherein the top surface is substantially coplanar with the major surface of the drain clip and wherein the bottom surface is substantially coplanar with a surface of the gate lead, a surface of the source lead, and the major surface of the source lead structure, and wherein the major surface of the source lead structure and the major surface of the drain clip form exterior surfaces of the semiconductor die package.

6. The package of claim 5 wherein the drain clip comprises copper.

7. A semiconductor die package comprising:

(a) a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface, and a drain region at the second surface;

(b) a drain clip having a major surface and being electrically coupled to the drain region;

(c) a drain lead electrically coupled to an end of the drain clip;

(d) a gate lead electrically coupled to the gate region;

(e) a source lead structure including at least one source lead and a protruding region having a major surface, and a die attach surface opposite the major surface of the source lead structure, the die attach surface being electrically coupled to the source region; and

(f) a non-conductive molding material encapsulating the semiconductor die, wherein the major surface of the drain clip is exposed through the non-conductive molding material.

8. The semiconductor die of claim 7 wherein a surface of the gate lead, a surface of the source lead, and the major surface of the source lead structure are substantially coplanar and are exposed through the molding material.

9. The semiconductor die of claim 7 wherein the drain clip comprises copper.

10. A method for making a semiconductor die package, the method comprising:

(a) providing a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface, and a drain region at the second surface;

(b) attaching a source lead structure to the source region and a gate lead to the gate region;

(c) attaching a drain clip having a major surface to the drain region;

(d) molding a molding material around the semiconductor die, whereby the major surface is exposed through the molding material,

wherein in (b) a source lead is part of the source lead structure and the source lead structure and the gate lead are part of a lead frame structure.

11. The method of claim 10 wherein the source lead structure includes a die attach surface.

12. The method of claim 11 wherein the source lead structure is formed by etching an area around the die attach surface.

13. The method of claim 10 further comprising attaching a drain lead to the drain clip using solder.

14. The method of claim 10 wherein the drain clip comprises copper.